Expanding the RISC-V Ecosystem, with PX5, IAR and SiFive

Bob Monkman (SiFive), with Bill Lamie (PX5) and Rafael Taubinger (IAR)

I recently had a great conversation with Bill Lamie, President/CEO of PX5, and Rafael Taubinger, Sr. Product Marketing Manager at IAR, regarding the recent port of the industrial-grade PX5 RTOS to the SiFive HiFive Rev B RISC-V development board (powered by a 32-bit SiFive RISC-V embedded microcontroller), using the IAR Embedded Workbench tools suite. I wanted to understand why Bill, who has been a serial innovator in embedded for decades, chose SiFive and IAR as the platform and development solutions, respectively, for his most recent venture. And, since I wasn’t yet familiar with the PX5 RTOS, I wanted to gain some insights into this latest technology. As a veteran of the RTOS market myself, I was super impressed that PX5 can be configured for minimal size, requiring less than 1KB of Flash and 1KB of RAM on 32-bit microcontrollers. The kernel features native POSIX threads API, making it portable and familiar to developers across the spectrum. The PX5 team has a particular focus on extensive validation and verification to enable use in safety-critical applications that require documented safety practices.

This was a big reason they used the ubiquitous IAR Embedded Workbench tools as well. The IAR solutions have been around for 40 years and have been used in countless safety-critical use cases with worldwide customers. The available functional safety edition is certified by TÜV SÜD and complies with the requirements of ISO 26262, IEC 61508, IEC 62304 and many more standards. IAR has a complete development toolchain with a highly optimizing compiler, and a great debugger that has been one of Bill’s favorite debuggers for the 20+ years he has been working with the IAR team. He told us that he recently used IAR’s code coverage analysis tools to ensure 100% code coverage in his own test framework for the PX5 RTOS, and the code analysis tool IAR C-STAT to meet MISRA and other coding standards established to deliver demonstrably high-quality code to the market.

Like a fast growing number of software vendors in the market today, both PX5 and IAR recognize that the RISC-V open ISA standard is gaining tremendous momentum, and they’re intent on delivering verified commercial support for RISC-V to their customers as the inevitable demand grows. I asked Bill why he chose SiFive as a RISC-V go-to-market partner, and the answer there was also consistent with what we hear every day from the ecosystem. PX5 sees SiFive as a leading RISC-V IP provider by multiple measures. They appreciate that SiFive’s founders are the same team who invented the RISC-V Instruction Set Architecture (ISA) in 2010, and that SiFive is a key thought leader and innovator in the evolution of RISC-V ISA in the overall ecosystem. SiFive is addressing a broad swath of market segments, including the safety-critical applications that PX5 is seeking to be ready to address. SIFive supports a single, consistent instruction set across all of our product offerings, increasing portability, while reducing costs and maximizing the energy efficiency, simplicity, security, and flexibility upsides that RISC-V offers.

This all makes great sense, and we at SiFive appreciate the enthusiasm and trust of software partners like PX5 and IAR, who are working together with us to deliver terrific value to the market.

For a free evaluation of the Px5 RTOS on the SiFive HiFive1 RevB board, please visit and scroll down to the SiFive section.

More information about PX5 RTOS is available here. For more information on IAR solutions for RISC-V, please visit.