In this blog, we’ll begin by introducing XNNPACK and exploring its current status on RISC-V platforms. Next, to bridge the technical gap for contributors, we will provide a step-by-step guide on integrating RVV-optimized microkernels into XNNPACK, using F32-GEMM (single-precision floating-point general matrix multiplication) as a practical example. Finally, we will highlight the performance improvements achieved through these optimizations. 

## XNNPACK and status of RVV backend

XNNPACK is a crucial library-based solution for neural network inference on ARM, x86, and RISC-V platforms. It serves as a low-level acceleration backend for machine learning frameworks, such as TensorFlow Lite, PyTorch, ONNX Runtime, and MediaPipe. XNNPACK enhances performance by decomposing operations into microkernels and applying target-specific optimizations for each architecture.

Historically, XNNPACK offered limited support for RISC-V Vector (RVV) extension, providing only a small number of RVV-optimized microkernels. As a result, RISC-V users often had to rely on generic C implementations. To utilize vector hardware, users can only rely on auto-vectorizers for parallelization or translation headers or tools to adapt intrinsics from other platforms.

To enhance AI inference performance on RISC-V, SiFive has contributed several RVV-optimized floating-point microkernels to XNNPACK. They are listed in Table 1. These contributions significantly improve performance, making RISC-V a more viable platform for neural network inference. We welcome everyone to join us in XNNPACK RVV backend contributions.

<div data-class="table-responsive"><table data-class="simple head">
<thead><tr><th>Microkernel Name</th><th>Description</th></tr></thead>
<tbody>
<tr><td>F32-GEMM</td><td>Float 32-bit general matrix multiplication microkernel</td></tr>
<tr><td>F32-IGEMM</td><td>Float 32-bit indirect general matrix multiplication microkernel which is for Convolution</td></tr>
<tr><td>X32-PackW</td><td>Float or integer 32-bit weight packing</td></tr>
<tr><td>F32-rmin</td><td>Float 32-bit reduced min</td></tr>
<tr><td>F32-rmax</td><td>Float 32-bit reduced max</td></tr>
<tr><td>F32-rminmax</td><td>Float 32-bit reduced min and max</td></tr>
<tr><td>F32-vadd</td><td>Float 32-bit binary addition</td></tr>
<tr><td>F32-vsub</td><td>Float 32-bit binary subtract</td></tr>
<tr><td>F32-vrsub</td><td>Float 32-bit binary reverse-subtract</td></tr>
<tr><td>F32-vmul</td><td>Float 32-bit binary multiplication</td></tr>
<tr><td>F32-vdiv</td><td>Float 32-bit binary divide</td></tr>
<tr><td>F32-vrdiv</td><td>Float 32-bit binary reverse-divide</td></tr>
<tr><td>F32-vmax</td><td>Float 32-bit binary max</td></tr>
<tr><td>F32-vmin</td><td>Float 32-bit binary min</td></tr>
<tr><td>F32-vsqrdiff</td><td>Float 32-bit binary squared-of-difference</td></tr>
<tr><td>X32_transpose</td><td>Float or integer 32-bit transpose</td></tr>
<tr><td>F32_raddstoreexpminusmax</td><td>Float 32-bit exponent for softmax operation</td></tr>
</tbody></table></div>

<center>Table 1. List of RVV-optimized microkernels contributed by SiFive.</center> 

## How to contribute the RVV microkernel to XNNPACK?

XNNPACK offers hundreds of microkernels to support neural network inference, with many neural network operations relying on one or more of these microkernels. For example, a `fully_connected` operator uses both weight-packing and GEMM (General Matrix Multiplication) microkernels. XNNPACK allows developers to implement target-specific microkernels, such as RVV (RISC-V Vector) versions of GEMM. If RVV and matrix extensions are available, alternative versions of GEMM microkernels can be developed.

Steps to contribute RVV microkernels:

1. **Identify the Operation and Relevant Microkernels** 
 Start by determining which neural network operation and data type to optimize. Then, identify the relevant microkernels for that operation. 
2. **Analyze the Microkernel Requirements** 
 Understand the data layout assumptions and structure of the microkernel. Reviewing the scalar version can reveal important details. Note that certain data layouts are adjustable using microkernel parameters. 
3. **Plan Vectorization Strategy and Select microkernel parameters** 
 Develop a vectorization strategy and decide the suitable microkernel parameters to maximize performance. 
4. **Implement the Target-Specific Microkernel Template** 
 Rather than directly implementing the microkernel in C/C++, XNNPACK designs to create a target-specific template to increase flexibility. For example, design a template that supports different LMUL settings or register-tiling configurations. Once the template is complete, use a Python-based generator to produce C/C++ microkernels. 
5. **Test and Benchmark the Microkernels** 
 Validate each generated microkernel with unit tests and benchmark to find the most efficient version. 
6. **Enable the Optimal Microkernel in Configuration** 
 After identifying the best-performing microkernel, enable it in the configuration to ensure the operation uses the optimal microkernel at runtime. 

#### Example: XNNPACK F32-GEMM optimization with RVV.

In this section, let’s take a floating-point fully_connected operation as an example. It is widely used in the Large language model and also the performance bottleneck. 
We follow the steps in the last section:

1. **Identify the Operation and Relevant Microkernels** 
 ![](https://images.prismic.io/sifive/Z1coc5bqstJ98PAS_Figure1.png?auto=format,compress) 
 Figure 1 The flow chart of floating-point fully_connected operation. 

 Based on Figure 1, there are two kinds of microkernels used in floating-point fully_connected operation. The first one is F32-GEMM. The other one is X32-PACKW, which stands for 32-bit weight packing. To simplify the article, we’ll focus on F32-GEMM in this blog. 
2. **Analyze the Microkernel Requirements** 
 The GEMM microkernel has two input data layouts that must be understood for optimal implementation. Additionally, there are four key microkernel parameters—`mr`, `nr`, `kr`, and `sr`—that define its operation. 
- **`mr`** and **`nr`** determine the maximum output size for each iteration through the `k` dimension. 
- The Left-Hand Side (LHS) input, `A'`, has a data layout of `[mr, k]`. This means the F32-GEMM microkernel processes only a partial segment of `A`, with the `m` dimension of the input always being less than or equal to `mr`. 
- The Right-Hand Side (RHS) input, `packed_weight`, has a layout influenced by `nr`, `kr`, and `sr`. Each `packed_weight` tile begins with `nr` bias values, followed by `[k, nr]` weight data, with its layout determined by `kr` and `sr`. 
- Figure 2 illustrates the data layout of `packed_weight` when `nr=8` and `kr=sr=1`. In this configuration, there are `round_up(n, nr)` `packed_weight` tiles. Each tile begins with `nr` bias values, followed by `[k, nr]` weights arranged in a row-major layout. 
 ![](https://images.prismic.io/sifive/Z1codJbqstJ98PAT_Figure2.png?auto=format,compress)

 Figure 2 The data layout of `packed_weight` when `nr=8` and `kr=sr=1` consists of `round_up(n, nr)` tiles. 
3. **Plan Vectorization Strategy and Select microkernel parameters** 
 Here, we aim to implement the outer product GEMM, setting `kr = sr = 1`. Our vectorization strategy focuses on vectorization along the `n` dimension of the packed weight and output matrices. We use `mr` vector register groups as accumulators, along with one vector register group to load the packed weights. The application’s vector length(`avl`) is determined by `nr`, which is calculated based on the vector length (`VLEN`) and vector length multiplier (`LMUL`) settings: 
<center>nr = VLEN * LMUL / 32. </center> 
 The values of `mr` and `LMUL` are defined by the input arguments of the template.

 Let’s explain the algorithm with an example: assume `mr = 7`, `nr = 64` (with `LMUL = 4`, `VLEN = 512`), and `k = 3`. After iterating through all values of `K`, we aim to produce `mr x nr` results.

 **Step 1 (Figure 3):**

 The first step is to load the `nr` bias values into the vector register group. These bias values are then duplicated across the `mr` accumulator vector register groups.

 ![](https://images.prismic.io/sifive/Z1codZbqstJ98PAU_Figure3.png?auto=format,compress)

 Figure 3 RVV F32-GEMM outer product algorithm(part1). 

 **Step 2 (Figure 4):**

 In each iteration over `K`, we load the `mr` scalar values into scalar registers (`a0` to `a6`). Then, we perform a vector load of the weight (`v_w_k`), followed by several vector floating-point multiplication-and-accumulation(`vfmacc`) instructions to compute the partial sum of the output. 

 ![](https://images.prismic.io/sifive/Z1codpbqstJ98PAV_Figure4.png?auto=format,compress)

 Figure 4 RVV F32-GEMM outer product algorithm(part2). 

 **Step 3 (Figure 5):**

 After iterating through all values of `K`, we obtain output results with dimensions `[mr, nr]`. These results are stored in `mr` vector register groups, with each register containing `nr` elements. Finally, the results can be written to the output.

 ![](https://images.prismic.io/sifive/Z1cod5bqstJ98PAW_Figure5.png?auto=format,compress)

 Figure 5 RVV F32-GEMM outer product algorithm(part3). 

 Steps 1 to 3 describe the procedure for calculating `[mr, nr]` results. This process needs to be repeated for all the tiles in `packed_weight` to obtain the entire output `[mr, n]`.

 Note: If input `N` cannot be evenly divided by `nr`, we need to modify the `avl` from `nr` to `N mod nr` when tackling the last output tile.
 

4. **Implement the Target-Specific Microkernel Template** 
 We developed an RVV f32-GEMM template that uses `mr` and `LMUL` as configurable parameters. 
5. **Test and Benchmark the Microkernels** 
 By generating code with various combinations of `mr` and `LMUL`, we could comprehensively test and benchmark performance across multiple configurations. 
6. **Enable the Optimal Microkernel in Configuration** 
 Based on benchmark results, we chose to enable an implementation with `mr=7` and `LMUL=4`, which maximizes vector register utilization and delivers optimal performance, in gemm-config. However, gemm-config is relatively complicated.If we want to enable RVV F32-gemm in configure. We also need to implement f32-igemm(indirect gemm) and corresponding x32-packw(weight packing) microkernels. 

## Performance Results

This section presents two types of experiments. The first involves microkernel-level benchmarks using the XNNPACK benchmark framework, while the second focuses on end-to-end model-level benchmarks through TensorFlow Lite. Both sets of experiments are conducted on the SiFive Intelligence X390 which supports RISC-V Vector and vector length (VLEN) is 1024\. Three settings are evaluated:

* **Setting 1**: Pure scalar microkernels without auto-vectorization 
* **Setting 2**: Pure scalar microkernels with auto-vectorization 
* **Setting 3**: RVV intrinsic microkernels 

#### OP-level

![](https://images.prismic.io/sifive/Z1coeJbqstJ98PAX_Figure6.png?auto=format,compress) 
Figure 6. XNNPACK microkernel benchmark: performance speedup under different configurations on the SiFive Intelligence X390. 

From the results in Figure 6, we observe that auto-vectorization provides only limited performance improvement. The primary reason is that most scalar code performs inner loop unrolling with a small size to emulate SIMD behavior commonly seen on x86 or ARM platforms. For example, in one of the reduced max microkernel calls, `xnn_f32_rmax_ukernel__scalar_u4_acc4`, the inner loop performs 4 binary max in parallel. This results in the auto-vectorizer generating code with a very small application vector length (AVL) of 4, which underutilizes the vector unit if vector length is large. To enhance auto-vectorization performance, rewriting the scalar source code is necessary. In contrast, the handwritten RVV-optimized code demonstrates better vector utilization and achieves a significant speedup compared to other approaches. 

#### End-to-end benchmark using TFLite

 ![](https://images.prismic.io/sifive/Z1coeZbqstJ98PAY_Figure7.png?auto=format,compress) 
Figure 7. Performance speedup of using TFLite with XNNPACK across different ML models. 

Figure 7 demonstrates performance speedups. It’s consistent with those observed in the XNNPACK benchmark. Specifically, transitioning from scalar to RVV achieves a speedup of over 45x, aligning with expected outcomes. Because the tested models are dominant to either F32-IGEMM or F32-GEMM. Both in the microkernel benchmark show a speedup of approximately 40x. Based on the performance results, we can conclude that optimizing XNNPACK RVV backend is a promising path. 

## Conclusion and Future Work

SiFive has provided optimizations for most of the critical single precision floating-point microkernels. The performance results are promising. However, XNNPACK isn't just for single precision floating-point neural network inference. There are still lots of microkernels that need to be optimized, such as the int8 version of GEMM, IGEMM and so on. We hope that RISC-V developers can join us in XNNPACK RVV backend contributions. 

#### Reference

XNNPACK [https://github.com/google/XNNPACK](https://github.com/google/XNNPACK) 
XNNPACK F32-GEMM pull request 1 [https://github.com/google/XNNPACK/pull/5893](https://github.com/google/XNNPACK/pull/5893) 
XNNPACK F32-GEMM pull request 2 [https://github.com/google/XNNPACK/pull/6411](https://github.com/google/XNNPACK/pull/6411) 
XNNPACK F32-GEMM pull request 3 [https://github.com/google/XNNPACK/pull/7035](https://github.com/google/XNNPACK/pull/7035) 
RISC-V Vector Extension specification [https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc\#vector-byte-length-vlenb](https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#vector-byte-length-vlenb)

SiFive Accelerates RISC-V Vector Integration in XNNPACK for Optimized AI Inference

**Pete Lewin, Director, Product, SiFive**

In June 2024, SiFive [announced](https://www.sifive.com/press/sifive-announces-4th-generation-of-popular-essential) the 4th generation of its [Essential](https://www.sifive.com/cores/essential) Product line. Products from the Essential family are already deployed in billions of consumer and IoT products including smartphones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more. This new release contains a wide range of iterations on the previous generations and numerous new features. The inspiration for the majority of these enhancements came from customer feedback. One specific example is the support for AMBA ACE, a protocol for bidirectional data coherency that enables customers to create systems with multiple clusters of Essential processors. 

What do customers cite as important aspects when they are selecting a processor? Well of course, power, performance, and area (PPA) are always important. Power efficiency is particularly important to applications such as smart sensors as they often need to run for years on a watch battery or very small solar cell. Additionally, there is often a particular focus on code density since memory size directly impacts system cost. There are also some concerns around security. As embedded systems become increasingly connected, and capabilities such as the ability to update firmware over the air, a whole new range of potential attack vectors need to be addressed. The new generation of Essential products improves on all these areas, with new code density extensions, advanced power management options, and the WorldGuard security architecture. You can check out this [video](https://www.sifive.com/cores/essential) from the RISC-V Summit in Munich in June 2024 for some additional details. 
![SiFive talk on Embedded applications for RISC-V](https://images.prismic.io/sifive/ZyFtqq8jQArT0AWN_Screenshot2024-10-29at4.19.36PM.png?auto=format,compress)


Quantifying performance is never straightforward. Clock frequency is one factor, but it’s far from the only one. To estimate real world performance, we run a range of benchmarks. Despite its well known limitations, the starting point is still often the Dhrystone benchmark due to its ubiquitous nature. The next level is often EEMBC benchmarks specific to the market segment. However, many customers know exactly what code they are going to run, and have some representative code from previous products. In this case, we have a range of simulation environments and FPGA platforms so customers can perform evaluations.

One of the big challenges I face as a product manager is assessing the feature requests from existing customers and prospects. What I have found useful over the years is to:

**Look for common themes**.
Try to look beyond the specific feature request and understand the “why” behind the request. What is the customer trying to achieve? This is important as there might be a more effective way to achieve the same objective.

Then it's a case of balancing engineering resources and timescales against other projects and making difficult tradeoffs… set against a backdrop of understanding specific markets and the competitive landscape.

Since our Essential Series offers a lot of flexibility, our customers can choose whether to use the Essential processor as a microcontroller in its own right, where it's the main processor in the system, or use it as a core alongside a different CPU. In the latter case, how it integrates with the rest of the system becomes a very important factor. Essential CPUs offer a wide range of interface options to give our customers more flexibility to suit their specific application needs.

To give a couple of examples about applications where some readers might not even think a processor would exist:
- Managing temperature in a soldering iron.
![Pinecil RISC-V based soldering iron](https://images.prismic.io/sifive/ZyFvQa8jQArT0AWp_Screenshot2024-10-29at4.25.34PM.png?auto=format,compress)
- In SSD controllers, performing “wear leveling” (working out where to store new files to ensure that the flash inside the system isn’t worn out too quickly) and implementing encryption on the storage device.

To address these and thousands of oher different applications and use cases, the [Essential](https://www.sifive.com/cores/essential) family covers quite a range of performance points, from a two stage pipeline up to dual issue, eight stage pipeline. SiFive has been focusing on the automotive market segment as well and this segment clearly has a lot of requirements around functional safety, and isolating certain system elements from each other. The automotive market has a reputation of being extremely slow moving. In part, this is driven by the obvious need to be focused on safety and quality, but it was also due to the somewhat static construction of the value chain and the evolutionary nature with which certain elements changed over time. The rapid adoption of electric vehicles, ADAS, and autonomous driving—along with the arrival of artificial intelligence—is driving significant change. 

In today's cars there are now a lot more actuators, a lot more sensors, and with them a lot more signals coming in that need to be processed and passed around the vehicle. Consumers are demanding multiple tablet-sized screens to interact with all this technology. This is causing fundamental changes to car architectures in order to increase reliability while reducing cost, weight, and power. Domain and zonal architectures have appeared to provide substantial improvements to those measures. At the chip level, this is causing a shift to fewer but larger, more powerful, multicore heterogeneous SoCs. These computing elements must be knitted together in a way that avoids compromising the functionality, reliability, and safety of the vehicle. SiFive is committed to providing IP that meets the latest [safety and security specifications](https://www.sifive.com/blog/sifive-enhances-risc-v-automotive-safety-leadershi), as well as delivering features like WorldGuard to segregate memory for specific workloads away from others. 

Unlike certain incumbents, SiFive is committed to continuing to evolve its entire processor portfolio to deliver improved PPA and innovative features. To that end, the planning behind the fifth generation of our Essential series is well underway. We see huge new opportunities for SiFive and our customers from growing the capabilities and characteristics of the low and mid-range of our portfolio.

And no technology blog is complete without a mention of AI! While a lot of the recent press around AI has been around large language models running on powerful servers, we have customers today implementing various AI capabilities on the fourth generation of Essential processors. These may be workloads like wake word detection, object detection  or fingerprint sensing. Part of the work around defining future generations of the Essential family includes ways to improve the effectiveness of these algorithms to enable the next generation of AI innovation in embedded systems. SiFive Essential products will play an important role in bringing AI to the edge across a wide variety of devices.



SiFive Leadership in the Rapidly-Growing Embedded Market

wearables-performance-news.jpg


**Ian Ferguson, Senior Director Infrastructure Segment Marketing, SiFive**

At the RISC-V Summit in North America this week, RISC-V International announced that the [RVA23 Profile](https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/) has been ratified. The fundamental objective behind RVA Profiles is to ensure software portability across hardware implementations.. This announcement reminded me of an important question that Krste Asanović, Co-founder and  Chief Architect at SiFive and Chief Architect of RISC-V International, brought up during his 2024 presentations at the [RISC-V Summit Europe](https://www.youtube.com/watch?v=_oLVPFQvJbI)in Munich and (more recently) at the RISC-V Summit China in Hangzhou. During these sessions, Krste tackled the (much asked) question: is RISC-V flexible or rigid? The answer is “Yes!”

![SiFive Party at Levi's Stadium](https://images.prismic.io/sifive/Zxp3mIF3NbkBYAPh_IMG_7417.jpg?auto=format,compress) 

On the one hand, RISC-V is very flexible. There are many different things a company or individual can do with it. RISC-V was intentionally designed in a modular way such that: 
- It can be extended.
- A core can be highly tuned for a specific application.

The “so what” from this approach is that the onus is then on that company or individual to deliver the software that supports these customizations. This approach has been successfully implemented by a number of companies, especially for black box applications such as solid state drives (SSD), where the provider of the SSD delivers all of the software that runs on that platform. What this means is that customizations to accelerate encryption functions, data movement, and wear leveling algorithms are not exposed to third-party programmers and programs.

RISC-V also enables companies to build a tightly controlled architecture, featuring (by design) mandated instructions and very few options. For companies that are building a core that is going to run tens of thousands of software packages, this rigidity is needed. The way this is achieved in the RISC-V community is with profiles.

When people raise the topic of fragmentation inside the RISC-V ecosystem, we find that they are confusing these two use cases. 

RVA23 mandates a number of capabilities including vector extensions and hardware virtualization support for implementing hypervisors. SiFive has already announced products in its [Performance](https://www.sifive.com/cores/performance) and [Intelligence](https://www.sifive.com/cores/intelligence) families that are compliant with the RVA23 Profile. One of the strong value propositions behind RISC-V as an open standard is the ability for customers to avoid vendor lock-in, so it is great to see other members of the RISC-V ecosystem aligning behind this key profile. Fundamentally, RVA23 aligns implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. Krste has also indicated that with RVA23 and other extensions that are currently in development or under review, RISC-V has caught up with other architectures. 

That said, processor architectures have to keep adding features over time to remain competitive. We run into this challenging chicken and egg situation where:
- Software companies won't support a new function it if nobody has it deployed in field systems; 
- And hardware folks will not deploy it if there is no software support. 

In the RISC-V ecosystem, there needs to be an agreement about new architecture features. RISC-V Profiles were designed to resolve this problem. Vendors get together and agree on the roadmap over time of when the features are going to be added to the instruction set. Software vendors must know the mandatory set of features that their software can rely on to be present. 

In addition to mandatory functions, profiles state optional elements. There are a few categories of these:

- **Localized options:** An example of this are cipher instructions since different ciphers are used in different locations around the world. Since RISC-V is a global standard, we embrace this diversity and enable customers to select the versions that work best for their use cases and go-to-market strategies.

- **Development options:** These are options that are early in the life cycle. Usually these relate to new features that are ratified and ones we intend to make mandatory in a subsequent profile. Given the timeline to support a new function, this approach enables the community to start to build support into products for this capability.

- **Expansion options:** These are capabilities that are very useful, but also tend to have a large cost. An example of this is matrix extensions. Not every system will want to have these mandated.

- **Transitory:** In this case, RISC-V is adding something in for developers to use as a stopgap or to experiment. 

RISC-V International and the broader community are also working on RISC-V Platforms. Platforms are a much bigger set of specifications. As an example in the server domain, this is nailing down how a system boots up, how it runs and, potentially most importantly, how these systems will be certified. I will share more about this in a subsequent blog.
![RISC-V International Logo](https://images.prismic.io/sifive/cfd727e8-24a8-49eb-a384-25dbd7c0d5a3_risc-v-logo.png?auto=format,compress)


banner_ai.png

Exploring the Ongoing Debate: Is RISC-V Rigid or Flexible?

**Martyn Stroeve - Senior Director, HiFive Programs, SiFive**

Reflecting on how far we’ve come since SiFive launched the world’s first RISC-V development boards back in 2016, it’s clear we’ve been on an incredible journey together with the RISC-V software community. Those early boards, like the HiFive1, were game-changers—true ignitors for the entire RISC-V revolution. Since then, SiFive has continued to innovate, releasing new boards every 2 years, adding more performance and features, pushing the ecosystem forward. 

When we launched the HiFive Unmatched Rev B in 2022, it quickly became the de facto choice for developers looking to create and optimize software for RISC-V.
As the RISC-V market has expanded, and with more companies now producing boards, we’ve had to push ourselves even harder.  For our next board, we have been focusing on quality, performance, and the developer experience. We are committed to ensuring our boards are the gold standard in the industry.

Providing a great out-of-the-box experience is a top priority. That’s why we’ve been taking some extra time with the upcoming [HiFive Premier P550 Board](https://www.sifive.com/boards/hifive-premier-p550). While we’re as eager as anyone to get this board into developers’ hands, we made the decision to ship with Ubuntu out of the box earlier in the year following several discussions with [Canonical](https://canonical.com/solutions/ubuntu-os) about how we could partner closer with them and create the best possible hardware and software combination with this exciting new board. The slight delay wasn’t a decision we made lightly, but we believe it was the best way to enhance the experience for the widest possible range of developers and ensure that everyone who buys this board has everything they need to hit the ground running.  In addition, it will also allow us to keep these boards up to date via the built-in over-the-air (OTA) update capability, which is a great feature.

![Board](https://images.prismic.io/sifive/Zw136oF3NbkBXaxW_HiFive-Premier-P550-Promo.png?auto=format,compress)

For those who aren’t familiar, the HiFive Premier P550 is a micro DTX form factor board that will be the highest performance RISC-V CPU development board in the world. Developed in partnership with [ESWIN Computing](https://www.eswin.com/en/index.php/about.html), this board features a quad-core P550 configuration that offers roughly double the single-threaded performance of other RISC-V boards available today—and about three times the performance of our previous generation, the [HiFive Unmatched](https://www.sifive.com/boards/hifive-unmatched-revb). It’s a significant upgrade for developers, offering a fully featured PC-style board that’s convenient and easy to work with.

Our vision is to build a development board program that’s not just the best in the industry but a model for others to follow. The “HiFive” program has been highly successful, however, scaling it by solely making more boards in-house wasn’t the optimal path. That’s why we’ve shifted our focus to leveraging our great customer base, using their experience to translate our IP into SoCs to bring more capable HiFive boards to a wider audience and of relevance to more market segments, quicker.

The name "HiFive" is a subtle play on SiFive and a universal gesture of celebration and camaraderie. We like to think of it as us giving developers a “high five” for their amazing work expanding the possibilities of RISC-V. As we shift to a more partner-centric approach, we aim to be “HiFiving” with partners a lot more in the future!

A critical factor in RISC-V’s success in markets beyond simple embedded chips  is the availability of optimized software, including hypervisors, operating systems, and middleware. SiFive is committed to supporting this by seeding units to select Independent Software Vendors (ISVs) and exciting new projects managed by [RISE](https://riseproject.dev/). If you have a project you believe deserves board support, we would love to talk to you more. 

Lastly, as we finalize the release of the HiFive Premier P550 development boards, we’re pleased to share that we have more future HiFive projects in the works with some amazing partners. Stay tuned for more updates!



HiFive Premier P550

HiFive-Premier-P550-Image-1.png

SiFive HiFive: The Vital Role of Development Boards in Growing The RISC-V Ecosystem + HiFive Premier P550 Update

**Ram Naik, SiFive Senior Product Director**

SiFive’s mission is to create the best computing solutions in the world so our customers  can deliver differentiated, best-in-class products. We do this not only by building great intellectual property (IP), but also by driving the RISC-V ecosystem forward. 
The open standard RISC-V architecture is the last instruction set architecture (ISA) that will ever matter. It’s not often that you can be part of a computing revolution; especially one that is revolutionizing systems as we know them. SiFive helps spur innovation across a broad community while ensuring our customers benefit from the evolution of our high-performance IP, ecosystem, extensions, and tools. 

RISC-V has firmly established itself in the embedded market across a diverse set of use cases. RISC-V is gaining traction in other markets including data centers, ADAS, consumer devices, space and automotive, as the main processor running the rich operating system and services. In these segments, the competition is x86 and Arm. The common trait across all these markets is the rapid change of system requirements which, in turns, creates an opportunity for disruption. SiFive understands the need to deliver solutions that are not just a few percentage points better than the offerings from the incumbents, but dramatically higher-performance, flexible solutions that our customers can tailor to specific applications. In this post, we’ll explore how SiFive’s latest data center offering meets the needs of demanding AI workloads.

At the core of strategy is the need to take a system level view. These systems require both highly capable general-purpose processing and optimizable-for-purpose AI performance. For the latter, SiFive has been delivering a set of Intelligence Processors that either couple tightly to a customers’ AI accelerator or, in the case of the newly announced XM Series, incorporates that functionality in addition to scalar and vector processing.

![RISC-V Summit diagram](https://images.prismic.io/sifive/ZwldooF3NbkBXVdK_blogPicture1.jpg?auto=format,compress) 

From the general-purpose processing perspective, SiFive launched the [Performance P870-D Processor](https://www.sifive.com/cores/performance-p870d) in August 2024. I find it extremely satisfying to see industry recognition of where the P870-D processor is positioned from a performance perspective, as shown on this slide from a presentation during the China RISC-V Summit in August 2024 by Semiinsights, an independent 3rd party company. 

 ![Diagram of P870-D](https://images.prismic.io/sifive/ZwldoYF3NbkBXVdJ_blogpic2.png?auto=format,compress)

This is a block diagram of the P870-D. You will notice that there are a lot of elements outside the P870-D CPU core itself. We get strong, consistent feedback from customers of the need for suppliers to offer system elements beyond the CPU core itself. As a result, for all of our processor offerings across the performance spectrum, SiFive provides a compute solution that includes not only the core clusters, but also the uncore agents, the IOMMU Gen2, and WorldGuard for security. This complete solution improves system development cycles and costs and reduces program risk.

The P870-D is a 64-bit Out of Order (OoO) core that is 6 wide, enabling up to 50% more single threaded performance compared to our prior generation P670 core. The P870-D microarchitecture is focused on single threaded performance with low power consumption, while also optimizing area. In this respect, our first generation solutions are very competitive with later generations of the Neoverse N series. 

The P870-D core cluster supports the AMBA CHI-E coherent interface, enabling customers to select any CHI-based third-party or customer-generated coherent network on-chip (NoC) solution. This support for a standards-based interface allows for easier integration into our customers’ existing fabric, offering core scalability which is critical for this segment. It is also core to our strategy of enabling chiplet based implementations as customers start to explore new SoC configurations that improve their flexibility to respond to new market opportunities.

The uncore agents enable the interrupt handling, MMU support, and trace/debug. The uncore agents offer a flexible routing to the clusters, enabling a variety of coherent interconnect topologies (supporting up to 256 cores).

WorldGuard is a fine-grain security model for isolated code execution and data protection. It provides SoC-level information control with advanced isolation control, based on multiple levels of privilege per world, and an unlimited number of worlds. In addition to the RISC-V Physical Memory Protection (PMP) that provides memory isolation for code and data manipulated by the CPU, WorldGuard expands hardware isolation to the whole SoC to protect caches, interconnects, arbitrary bus masters, memories, and peripherals. In summary, WorldGuard is a very practical, scalable solution for real-time SoC partitioning.
The second generation IOMMU provides a split version of the IOMMU, offering a distributed architecture that supports up to 8 IOTLB to reduce bandwidth congestion.  This feature extends the scalability of IO devices required for datacenters and networking. The second generation also has support for 57-bit virtual addresses for memory intensive workloads or multiple concurrent workloads.

Finally, P870-D’s reliability, availability and serviceability (RAS) provides protection for on-chip memories,  processor architectural states (register files, control and status registers(CSR)), and key structures of the datapath including interconnect and shared cache controllers. The P870-D RAS solution provides frameworks to configure and report errors in a way that is compatible with the RISC-V standard specifications.

SiFive’s P870-D offering, augmented with SiFive’s Intelligence AI products, will be leading the charge in the transformation of data center architecture towards one that is open and standards-based. This approach allows customers to innovate faster and in a way that more efficiently tracks the unique requirements of their intended use case. A key catalyst contributing to this transformation is the Server Platform Specification authored by the RISC-V server task group. The specification defines a standardized set of hardware and software capabilities that system software (such as operating systems and hypervisors) can rely on being present in a RISC-V server platform. The end state will be a single binary OS image distribution model that ties together hardware (SoC), firmware, and security specifications. End customers continue to demand choice and what this enables is for companies to avoid lock-in to a particular RISC-V implementation since all suppliers that are pursuing this segment are engaged in creating solutions that conform to this specification. 

SiFive is bringing all these elements together to open up new opportunities for AI innovation in data centers, with P870-D leading the charge. We look forward to sharing more details in the months ahead.



SiFive 870-D, RISC-V datacenter processor

Datacenter innovation with 870-D

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SiFive; Empowering A New Era of Data Center Innovation 

SiFive outlines how we optimized & deployed Llama on the SiFive Intelligence X390 platform, the future computing platform for AI/ML workloads.

LLM Optimization and Deployment on SiFive RISC-V Intelligence Products

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**John Ronco SVP Product**

In case you missed it at the 2024 Samsung Developer Conference today, our partners at Samsung Visual Display discussed the work they have been doing to port the Tizen operating system to RISC-V. Tizen is an open-source operating system (OS) that is used in many Samsung smart T.V.s and it makes sense that they would look to the fast growing, global open-standard RISC-V to develop future systems. The presentation showed the results of efforts at both companies to expand the capabilities of the already robust Tizen approach. At the event they also demonstrated a T.V. running on RISC-V and using a SiFive Performance P470 based core.  

![Samsung TV running Tizen on SiFive P470](https://images.prismic.io/sifive/Zv7Lo7VsGrYSwWIv_IMG_6818.jpg?auto=format,compressuaeeLVsGrYSvX2t_XMEnablesHighScalability.png?auto=format,compress) 

SiFive and RISC-V products have many current and future applications in consumer devices and across the IoT.  As major software ecosystems  continue to optimize for RISC-V we expect to see much continued progress in the months ahead and it makes sense also that an important OS like Tizen would include RISC-V capabilities. 

The low power, flexibility and performance benefits of SiFive’s Performance cores are ideal for products like Smart TVs and we are pleased to collaborate with Samsung on ways to bring RISC-V to Tizen in the future.   Our global hardware and software teams have worked closely with Samsung teams to understand the challenges and today’s announcement is the culmination of a lot of great work by teams at both companies. 

The  presentation  marks an exciting milestone and highlighted an important new piece of the inevitable RISC-V ecosystem.  
 




Samsung using SiFive P470 to bring RISC-V to TIzen

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Samsung Highlights Work to Bring RISC-V to Tizen 


At our recent SiFive Day event, SiFive’s CEO [Patrick Little](https://youtu.be/E_mHdPxnyRo?si=lKu-Sm4ZVeewV1YG) explained that “AI and RISC-V were made for each other.” The open RISC-V standard frees developers from the restrictions of proprietary compute, giving them more flexibility to innovate. RISC-V efficiently supports specialized computing engines including mixed-precision operations, and developers can further customize solutions with vector instructions and specialized AI extensions. Additionally, RISC-V has a widely supported software ecosystem.

![XM Series](https://images.prismic.io/sifive/ZuaeeLVsGrYSvX2t_XMEnablesHighScalability.png?auto=format,compress)

Last week SiFive rolled out our [Intelligence XM Series](https://www.sifive.com/cores/intelligence) to help companies accelerate high-performance AI workloads for edge IoT, consumer devices, next generation electric and/or autonomous vehicles, data centers, and beyond. The XM Series integrates scalar, vector, and matrix engines to enable extremely memory bandwidth-efficient compute. Featuring four X-Cores per cluster, a cluster can deliver 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz. With its scalable design, customers can build industry leading levels of performance while still optimizing efficiency since SiFive offers extremely high performance per watt. 

Watch Krste Asanovic, SiFive Founder and Chief Architect, discuss "why RISC-V for AI" and give an overview of the new XM Series in the video below or keep reading to learn more. 

[Watch Krste Asanovic talk about SiFive Solutions for AI](https://youtu.be/gKojvV1Y-EE?si=h3nMy23LbersMZiQ)

As Asanovic shared, “a flexible and scalable hardware solution is needed to maximize AI software investment.” He noted that there is a “tremendous rate of evolution of AI models, the structure of the models, and the data types they use” so companies need the flexibility to tailor their solutions for market-specific constraints. There is 1TB/s of sustained memory bandwidth per XM Series cluster. Clusters can access memory via a high bandwidth port or via a CHI port for coherent memory access. Additionally, the XM Series supports systems incorporating no host CPU or ones based on RISC-V, x86, or Arm.

The XM Series is the first IP from SiFive to include a highly scalable AI matrix engine, helping customers speed up time to market. The XM Series complements SiFive’s existing X series portfolio in the SiFive Intelligence family, which is designed to connect efficiently to customers’ AI engines. SiFive will continue to invest in advancing both the XM and X product serie. SiFive sees AI as a capability that will be added to virtually all systems, from sensors to supercomputers, so we’re offering our customers more choices so they can choose the IP best suited to their roadmap and market constraints.

To learn more about the [XM Series](https://www.sifive.com/cores/intelligence-xm-series) or other AI solutions from SiFive, [contact sales](https://www.sifive.com/contact-sales).

**David Miller, Head Corporate Communications**

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AI Workload Acceleration with SiFive’s New Intelligence XM Series 

I was fortunate enough to attend the RISC-V China Summit in Hangzhou in August. As a premium sponsor, SiFive had a large presence at the show with a booth in the exhibition hall and several executive presentations.  The inspiration for writing this blog was when a great friend of mine asked me to compare and contrast this event with other recent RISC-V events held in North America and [Europe](https://www.youtube.com/playlist?list=PL85jopFZCnbMC17gv4DLSY7vo4oTjBWM2). My high-level response was;

**Scale**; Quite simply, this event was significantly bigger. I have yet to see the actual numbers, but it felt like two to three thousand people attended, which would make it approximately 2x the size of the 2023 RISC-V North America summit. 

**Addressing Current Commercial Challenges**; All RISC-V events feature a mix of academia and enterprise presentations, booths and conversations. I felt that while the European event was more skewed toward academia, this one was more centered on commercial discussions. Revenue-generating projects that needed to be addressed with silicon, software and intellectual property in a relatively near-term timeframe.

**China-Specific Innovation**; The organizers had real-time translation of the presentations from Chinese to English and vice versa. It did a pretty good job but wasn’t perfect. At one point in a presentation about RISC-V vector processing the translation (I suspect AI based) translated the sentence into “Victor Putin”. While I was clear they weren’t talking about the Russian president, it helped me follow along and make sense of quite detailed technical presentations discussed in a language I am not familiar with. There were a number of local semiconductor companies present. Additionally (and I view it as a measure of the direction this region is taking and commitment behind RISC-V), there were a significant number of software and systems companies. It was impressive to see so many new companies at the show. This shows the true international force that the RISC-V community has become..

One of the big transitions that has been underway since I last visited China in 2018 is in the automotive sector. 
Electric vehicles are now outselling traditional engine-based vehicles in cities like Shanghai and Shenzhen (the weather in more northerly Beijing means this milestone has yet to be reached)
The known brands from the west are being consumed by brands like Geely, BYD, Roewe, Wuling, Chang'An and Baojin. Not household names to many of us a set of ecosystem providers are establishing themselves to service these manufacturers, including Tier 1 and Tier 2 suppliers.
What is consistent with the other events was that RISC-V’s increasing presence in embedded markets is undeniable, and while it continues to gain market share,  the ecosystem is now focused on increasing the momentum toward higher value markets, the penetration of which requires an ecosystem of aligned technologies to coalesce. This drove a recognition that there was a need to collaborate across competition boundaries, across country borders and across industries.
![Calista from RISC-V International](https://images.prismic.io/sifive/Zs-hGUaF0TcGJfiB_IMG_1221.jpg?auto=format,compress)



Making RISC-V a truly viable option for other, higher value applications is going to require the community to fully embrace and communicate the value proposition of RISC-V in key ways;
It’s rigidity; [“Profiles”](https://github.com/riscv/riscv-profiles) (a set of instructions) that must be incorporated into an SoC in order to run specifical rich operating systems and associated system level software pieces.
It’s flexibility; Enabling innovation since there is a need to deliver significantly better capabilities in order to convince customers of the merits of changing.
To that end Krste Asanovic, the Chief Architect behind RISC-V, gave an update on the RVA23 profile which is in the process of being ratified. 
![Krste Asanovic Inventor of RISC-V and Founder SiFive](https://images.prismic.io/sifive/Zs-lbkaF0TcGJfj6_IMG_1224.jpg?auto=format,compress)




It was pleasing to see SiFive’s [Performance P870-D processor](https://www.sifive.com/cores/performance-p870d) recognized by an independent researcher as being the performance leader for RISC-V technology that is focused on the datacenter segment. It is clear that a number of other companies are focused on driving into that segment. SiFive clearly has to continue to work closely with customers and execute on our roadmaps in the Performance Processor Line to remain a leader. 
![SiFive presentation](https://images.prismic.io/sifive/Zs-kI0aF0TcGJfjC_IMG_1239.jpg?auto=format,compress)



The other widely held rhetoric at the event was that just like x86 became the architecture for computers and Arm became the standard for smartphones, that with its flexibility and scalability RISC-V will become the defacto standard for Artificial Intelligence.

To conclude, while significant progress has been made in driving adoption of RISC-V into a diverse set of applications, the community isn’t resting on its laurels. There is significant work needed to broaden RISC-V’s reach into new markets. That is going to take collaboration, patience and a whole lot of innovation to disrupt the incumbents but the excitement and enthusiasm at this event gave me a lot of confidence that RISC-V is headed nowhere but up. Our event focus now turns to the event in Santa Clara in October. We are excited to meet customers, prospects and partners there. For information about the event and registration details, [click here](https://riscv.org/event/risc-v-summit-north-america-2024/).   

**Ian Ferguson is Senior Director, Infrastructure Segment Marketing for SiFIve**

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RISC-V World Tour; Munich, Hangzhou, Santa Clara and Russia??

One of the primary motivations behind my decision to join SiFive was the opportunity to define, articulate and execute our go-to-market initiatives for a range of high value market segments. Several analysts have created their estimates of market share growth into these segments including Omdia (see chart below). SiFive has strong momentum, but, to me, the infrastructure/datacenter segments are particularly exciting. 
![Omdia graph](https://images.prismic.io/sifive/Zrpy50aF0TcGI38F_Slide1.jpeg?auto=format,compress)

I know from my time that engaging in a new market segment is a challenging proposition. There needs to be a commitment from the company to see the course with the creation of a series of products for that segment, investment in nurturing an ecosystem and to pivot based on feedback received from customers, changes in the market dynamics and the competitive landscape.

I am thrilled to be part of a cross functional team that is releasing the [P870-D product](https://www.sifive.com/cores/performance-p870d). We have delivered early versions of the CPU core to help customers get started on their system-on-chip developments and will be releasing a final version later this year.

Let’s take a step back as to why I feel now is the time for a new disruption to occur in data center architectures. At a high level, I see three primary motivations.

1. Increased use of open-source APIs and foundational software across use cases. This enables new technologies to participate more easily than having to rely on 3rd parties to make the decision to support a new processor architecture. This is one of the challenges that Arm has faced in participating in the Enterprise Computing segment as so much software remains optimized for only x86. In the cloud domain, the RISC-V ecosystem still has a long way to go. I see us now moving from a “ported to” stage into a “fully optimized-for” RISC-V phase. Primarily, this work is being executed in the [RISE organization](https://riseproject.dev/) where SiFive is an active participant. RISE is dedicated to enabling a robust software ecosystem specifically for application processors that includes compilers, toolchains, system libraries, kernel, virtualization, programming languages, Linux distribution integration, and tools for debug and profiling. 

2. Sustainability, cost and/or performance concerns are driving need for innovation, and one size does not fit all. Fundamentally, the disruption (which is causing a reason for companies to look at alternatives) here is AI. Training a large language model like OpenAI’s GPT-3 uses nearly 1,300 megawatt-hours (MWh) of electricity, the annual consumption of about 130 US homes. According to the IEA, a single Google search takes 0.3 watt-hours of electricity, while a ChatGPT request takes 2.9 watt-hours. If ChatGPT were integrated into the nine billion searches done each day, the IEA says, the electricity demand would increase by 10 terawatt-hours a year —- the amount consumed by about 1.5 million European Union residents. The other disruption is the desire to shift decision making to the edge as opposed to processing occurring exclusively in the cloud. This creates the need for extremely stringent cost, power and performance targets to be met.

3. A desire from the industry for increased resilience to supply chain disruption. Solutions must remain valid for years in order to generate the desired total cost of ownership benefits. The fact that RISC-V is an open standard AND that everyone is empowered to participate in advancing the architecture is a major benefit
There is more detail in this interview I conducted with betanews in July 2024.

For more information, check out my interview I conducted with [BetanNews](https://betanews.com/2024/07/03/how-risc-v-is-changing-the-server-market-qa/) in July 2024.


The P870-D processor is a purpose built processor for datacenter applications as part of a broader family of processors that are focused on use cases that demand higher performance. It is important to add protections on memories,  processor architectural states (register files, control and status registers (CSR)) and key structures of the datapath including interconnect and shared cache controller to deliver the system resilience needed to handle errors.

The inclusion of the CHI interface, coupled with partnerships with providers of complementary network on chip (NoC) technology such as Arteris enables our mutual customers to scale up systems into hundreds of cores, with on a single piece of silicon or using various die to die connectivity strategies for chiplets.

![System diagram](https://images.prismic.io/sifive/Zrpy00aF0TcGI38D_Slide1.jpeg?auto=format,compress)

As opposed to performance at any cost, SiFive continues to look at performance inside specific size and power constraints. The result is a processor that enables the creation of infrastructure SoCs with higher compute density than using incumbent approaches. This is appropriate for workloads that require the execution of many compute tasks in parallel such as including native RISC-V build servers, video streaming, storage, and web appliances.

The real system benefits come when this technology is combined with dedicated AI processing.

This combination of general-purpose computing (which can harness foundational open-source software) along with customized hardware is what I believe is the key combination of technology critical to addressing the power and cost challenges listed above. 

From a software perspective, our target datacenter segments harness a combination of open source software and first party software. The foundational open source software elements already exist for RISC-V and I am seeing increased acceleration of “optimized-for-RISC-V” components due to the collaborative efforts across the community such as RISE. The capabilities of the P870-D processor are well aligned with RISC-V International work in this area as well as the platform specification work that is underway, enabling customers to reuse in their own designs, saving time, cost and increasing the chances of program success.

![SiFive Solutions](https://images.prismic.io/sifive/ZruUfkaF0TcGI5zz_Slide1.jpeg?auto=format,compress)

Embracing AI in a cost-, power- and future-proofing way, requires the creation of innovative solutions. We feel that the people that are in the best place to define those solutions are those that are closest to the specific use case. This is one of the fundamental advantages that RISC-V brings and an area that SiFive is focused on enabling as effectively as possible. Today’s announcement represents a solid first step. Our roadmaps for both the performance and intelligence product lines will be driven based on inputs from customers as they look to deploy P870-D based chips and systems in 2025 and beyond. 

If you’d like to hear more about these solutions contact your [sales](https://www.sifive.com/contact-sales) representative. 


Explore the latest developments in SiFive's journey to disrupt data center architectures with the new P870-D processor from Ian Ferguson.

RISC-V for the Datacenter: Introducing the P870-D - SiFive Blog

RISC-V for the Datacenter: Introducing the P870-D

SiFive has a global footprint, working with the world's largest semiconductor manufacturers, automakers, global hyperscale data centers, and consumer device companies. It’s no surprise then that we’re frequently at industry shows and events around the globe. We recently participated in shows across Asia, Europe, and the U.S., and we’re off to RISC-V Summit China next. Read on to learn more about our latest activities and what’s ahead. 

SiFive will be talking about RISC-V and SiFive’s roadmap and momentum at the [RISC-V Summit China](https://riscv.org/event/risc-v-china-summit/), taking place from Aug. 21-23 in Hangzhou. In the exhibition hall we’ll be showcasing SiFive’s new state-of-the-art RISC-V development board, the [HiFive™ Premier P550](https://www.sifive.com/boards/hifive-premier-p550). At our booth we’ll also demonstrate our HiFive Unmatched Rev. B boards, which, given a host of new boards coming this fall, are now discounted to [$299](https://www.mouser.com/ProductDetail/SiFive/HF105-001?qs=Imq1NPwxi75JBw6ulD0quQ%3D%3D) —an incredible deal for a high performance development platform in a standard PC form factor. 

**SiFive’s executives will deliver a number of talks at RISC-V Summit China**:

Krste Asanovic, Co-Founder & Chief Architect, will discuss the impressive momentum across the RISC-V ecosystem and share thoughts on where the architecture is headed.

Jack Kang, SVP, WW Business Development, Sales, and Customer Experience, will provide an update on SiFive’s roadmap, talking about our recent embedded announcements, our latest boards, and some of the innovative products we offer for the China market. 

Rocky Zhang, Principal Field Applications Engineer at SiFive China, will be speaking about SiFive’s products for AI workloads. 

To learn more about what SiFive has been up to, check out our sessions from the RISC-V Summit Europe which are now on YouTube. Here are some of the highlights: 

During Krste’s [state of the union keynote](https://www.youtube.com/watch?v=_oLVPFQvJbI&t=26s), he shared some of the latest updates in the RISC-V ecosystem. 

Pete Lewin, Embedded and Automotive Product Director, [discussed](https://www.youtube.com/watch?v=tdu_SA2j1Fs) SiFive’s Essential product line, which is designed to optimize power and performance in a range of devices. 
 
Dany Nativel, Senior Director, Product Marketing, gave a [lightning talk](https://youtu.be/qse04mbQBiI?feature=shared) about the HiFive™ Premier P550.  

Additionally, Nathan Egge at Google presented recent work from RISE about harnessing [RISC-V vector extensions](https://youtu.be/asRnBcn5VKs?feature=shared_) to optimize a software video decoder. SiFive worked extensively behind the scenes with Nathan and others across the RISC-V community to support this work and we are extremely proud of the results and the learnings that came out of this project.

Watch for a couple of new important product announcements soon. Additionally, we’re gearing up for the RISC-V North America Summit in October, where we are the sponsor of the Developer Zone.

To stay up-to-date about SiFive’s news and activities, make sure to follow us on X and [LinkedIn](https://www.linkedin.com/company/sifive/posts/?feedView=all). 
 


What’s Coming Up Next for SiFive

The automotive market requires high levels of quality and safety. With the rapid increase in the number of chips and electronic systems in vehicles—there are as many as 3000 or more chips in some cars—the need for safety and the ability to test and certify these systems has become more challenging and more critical. Recognizing the importance of quality and safety early on, SiFive formed a team of world leading experts in automotive functional safety (FuSa) to empower our customers to swiftly deliver safe, secure and certified products for connected vehicles. These functional safety products are also beneficial for many other markets, including aerospace and defense. In this blog we’ll share more information about functional safety and will talk about how SiFive is integrating it into our broad portfolio.

#### What is functional safety?

In the automotive world, functional safety is all about ensuring that electronic systems in vehicles do not pose a risk or harm people, even in the case of a failure. ISO 26262 is the international standard that defines the requirements for functional safety. Achieving certification is a complex process involving rigorous testing, analysis, and documentation to minimize the risk of potentially dangerous malfunctions.
 
The standard defines functional safety as the “absence of unreasonable risk due to hazards caused by malfunctioning behavior of the electrical/electronic systems.” Functional safety standards like ISO26262 use safety integrity levels as a means to quantify what a reasonable risk could be in a vehicle system. The automotive safety standards define an automotive safety integrity level classification, ranging from ASIL A (which is the least stringent) to ASIL D (which is the most stringent). 

To meet the required integrity level of functional safety standards and adequately mitigate risks, companies need to  fulfill process requirements (methods and techniques) and/or add functional features to detect and control failures.

Functional safety is focused on preventing two kinds of failures:

**Systematic failures**, which are present from the beginning (e.g design bugs) and can manifest themself in the final product. They are avoided by adopting a robust development; the correspondent risk mitigation is quantified by the systematic capability.

**Random hardware failures**, which are due to events randomly appearing on the field, sometimes made possible by degradation (aging). They are detected or controlled by specific features called safety mechanisms and quantified by the hardware random (or diagnostic) capability.

#### SiFive approaches safety with a divide and conquer approach.
SiFive addresses the complexity of automotive functional safety with a divide and conquer approach. We recognize that a safe vehicle is the result of a collaborative effort across the entire supply chain.

Our strategy begins by embedding safety into the hardware IP that we design. This not only ensures the integrity of our IP, but also empowers our customers to confidently integrate these components into their larger systems. This divide and conquer approach allows each supplier to focus on their area of expertise, ultimately contributing to the creation of a holistically safe vehicle.

Here's how it works: the integrity level allocated to a specific system (e.g. the breaking system) can be decomposed with an integrity level that each and every component on the system has to achieve. This is a typical approach in distributed development. This allows different teams or suppliers to focus on independently achieving the safety requirements for their specific components. SiFive ensures both random hardware faults (through safety mechanisms) and systematic faults (through rigorous development processes) are addressed in our products.

By taking this methodical and collaborative approach, SiFive simplifies the complex task of building safe vehicles. It's a win-win: we create safer, more reliable components, and our customers can seamlessly integrate our certified IP into their systems, accelerating the development of safe, high-quality vehicles for the end consumer.

#### So why is this so important?

As vehicles become more reliant on electronic systems for everything from engine control to advanced driver assistance systems, the importance of functional safety cannot be overstated. Failures in these systems could have catastrophic consequences resulting in loss of life, along with disastrous implications for the manufacturer.

Furthermore, as the industry moves towards autonomous vehicles, the safety of electronic systems becomes even more important when  the driver is not taking control and mechanical systems are replaced with digital ones. These systems also need to last in a vehicle for decades. As a result, electronic systems in autonomous vehicles are very complex, with many interactions between other systems and they have to work as expected in many different conditions, even in cases not imagined during the initial design.

Another challenge is that consumer vehicle manufacturers are very sensitive to cost, particularly as the overall cost of electronics is rising. In order to be competitive, or even affordable, the cost of the electronic system needs to be relatively low. To keep costs down, it is not possible to solve the safety problem by duplicating or triplicating the systems, which is done  in avionics and aerospace applications.

Without the right procedures in place, implementing systems with high performance and high complexity at low cost increases the risk of failures. For instance, using advanced technology nodes can lead to new types of faults, and artificial intelligence leads to unpredictable behavior. While combining more functions on the same system (e.g. IVI and ADAS) reduces cost, this creates potential interference that requires a lot of attention.

In short, functional safety isn't just a technical matter; it's about protecting lives and building trust in the increasingly complex technology that powers our vehicles.
 
#### Accelerated development and time to market
SiFive enables system integrators to leverage our pre-certified IP, developed as a Safety Element out of Context (SEooC), to significantly reduce development time, effort, and risk. This saves system integrators from having to do audits and map their supplier's process to the requirements of ISO 26262. This makes it easier and faster to develop a safety case for incorporating the IP into broader systems. 

Pre-certified IP comes with complete documentation on what has been analyzed, and how and what needs to be done at the system level.

Key benefits to the customer include: 

**Risk reduction:** The rigorous certification process gives system integrators confidence and peace of mind about the quality and reliability of the IP that is integrated into their system. The system integrator knows what has been done and what needs to be covered, and there is no risk of discovering gaps late in the development cycle.

**Cost/effort savings:** Pre-certified IP has gone through the certification process and so the integrator does not need to repeat it and can concentrate their effort on the remaining part of the system and what they do best. Having third party IP in the certification scope of a system can be very complex due to the limited knowledge and information that the user typically has, so we help to avoid this with our pre-certified IP.

**Development time reduction:** The certification activities for the pre-certified IP are already done and properly documented, significantly reducing development time and effort. 

**Competitive advantage:** SiFive's certified IP provides customers with a competitive edge in the automotive market. Additionally, SiFive is committed to staying on top of the latest standards and we are active participants in standards bodies to help identify new techniques and methodologies, better understand the intention of standards, and to ensure the latest techniques and methodologies are achievable. With this commitment to safety we’re bringing our customers peace of mind and serving as a valuable resource for them. 
 
#### SiFive functional safety leadership
By offering pre-certified IP as SEooC, we’re ensuring that the core building blocks of automotive systems are developed following rigorous development processes which are ASIL D compliant. These processes are the cornerstone of preventing systematic failures. This IP is also designed with appropriate safety mechanisms to provide protection against random hardware faults, supporting applications to meet hardware integrity up to ASIL B and ASIL D.

These processes are independently reviewed and audited by a third-party (TÜV SÜD) as part of the functional safety assessment of the [SiFive Automotive products](https://www.sifive.com/cores/automotive). These products are certified to meet ASIL D systematic integrity and achieve up to ASIL B and ASIL D hardware integrity.
Designated products have a dedicated safety package to document everything the user needs to properly use them in a safety related system, including:
A safety manual
Safety analysis report including the Failure Modes, Effects, and Diagnostic Analysis (FMEDA) and the Dependent Failure Analysis (DFA)
Development Interface Agreement (DIA)

#### Which SiFive products are certified?
Today the following SiFive automotive products have successfully obtained ISO 26262 certification:

**[E6-AB](https://sifive.cdn.prismic.io/sifive/Zp9ptB5LeNNTxamy_Z101255320001Rev.00.pdf)**: A 32-bit embedded processor ideal for real-time applications requiring ASIL B hardware safety integrity.
 
**[E6-AD](https://sifive.cdn.prismic.io/sifive/Zp9ptR5LeNNTxamz_Z101255320002Rev.00.pdf)**: A 32-bit processor designed for advanced driver-assistance systems (ADAS) and other demanding safety-critical applications. 

**[E6-AS](https://sifive.cdn.prismic.io/sifive/Zp9ptR5LeNNTxam0_Z101255320003Rev.00.pdf)**: A 32-bit processor supporting split-lock functionality, targeting ASIL D integrity level in lock-mode. 

**[S7-AD](https://sifive.cdn.prismic.io/sifive/Zp9pth5LeNNTxam1_Z101255320004Rev.00.pdf)**: A 64-bit processor optimized for safety-critical functions that delivers exceptional performance for zonal controllers and other complex automotive systems.

SiFive also recently became the [first supplier to achieve ISO/SAE 21434:2021 product certification](https://www.sifive.com/blog/sifive-becomes-first-ip-supplier-to-achieve-automo), which provides a comprehensive framework to identify, assess, and mitigate cybersecurity risks across the supply chain. 

To sum it up, SiFive’s certified IP lowers risk and development time. By utilizing SiFive's certified SEooC IP, customers can:

**Lower risk**: Significantly reduce the risk of product recalls, accidents, and legal liabilities.

**Increase confidence**: Gain confidence in the safety and reliability of their products.

**Streamline certification**: Simplify the overall certification process for their components/systems.

For more information, [contact your SiFive sales representative or reach out through our website](https://www.sifive.com/contact-sales).



The automotive market requires high levels of quality and safety. In this blog we’ll share more information about functional safety and will talk about how SiFive is integrating it into our broad portfolio.

SiFive Enhances RISC-V Automotive Safety Leadership with Critical Functional Safety Certification

automotive-solutions-sifive.jpg

In the era of software-defined vehicles (SDVs), cybersecurity isn't just a buzzword; it's a critical necessity. SDVs are increasingly vulnerable to cyberattacks thanks to their interconnected systems,  huge size of software  and vast amounts of data being generated and processed. These attacks could compromise safety, privacy, and even a vehicle's functionality and have huge implications to brand reputation. To help mitigate these risks, SiFive is laser focused on cybersecurity and recently achieved ISO/SAE 21434:2021 product certification. 

[View our Cybersecurity Assurance Program Certificate](https://sifive.cdn.prismic.io/sifive/Zp7BDB5LeNNTxZBg_ULCAP_P110.pdf)

For more information on this milestone and SiFive’s deep commitment to automotive security, check out our Q&A below with SiFive’s Priyanka Viswanathan, director of quality, functional safety and cybersecurity, and Yann Loisel, Principal Security Architect.

**What is ISO/SAE 21434:2021 and why is it a big deal that SiFive received ISO/SAE 21434:2021 certification?**
 
ISO/SAE 21434:2021, the premier international standard for automotive cybersecurity engineering, provides a comprehensive framework to identify, assess, and mitigate cybersecurity risks across the supply chain. The standard covers the entire lifecycle of a vehicle, from concept to decommissioning. Additionally, ISO/SAE 21434:2021 satisfies the UNECE WP.29 R155 regulation, which ensures that cybersecurity management systems (CSMS) take a systematic approach to risk management.
Although UNECE WP.29 R155 compliance is mandated only in the European Union, Japan, and Korea, the requirements of the standard are used by most car manufacturers (OEMs) across the globe as a best practice so they can design vehicles to meet the requirements of markets across the globe.

SiFive is the first IP provider to achieve ISO/SAE 21434:2021 product certification, validating that our automotive solutions are developed to the requirements of CSMS (audited and certified by a third party to make sure that the CSMS meets the requirements of ISO/SAE 21434:2021) and are equipped to resist the evolving threat landscape. Our automotive customers can design with confidence knowing that we have implemented the highest industry standards throughout the design, development, and deployment of our products. 

**Which of SiFive’s products have ISO/SAE 21434:2021 certification?**

SiFive not only received ISO/SAE 21434:2021 certification for our CSMS, SiFive also completed ISO/SAE 21434:2021 assessments on our RISC-V based SiFive Automotive products:

**[E6-AB](https://sifive.cdn.prismic.io/sifive/Zp9ptB5LeNNTxamy_Z101255320001Rev.00.pdf)**: A 32-bit embedded processor ideal for real-time applications requiring ASIL B hardware safety integrity.

**[E6-AD](https://sifive.cdn.prismic.io/sifive/Zp9ptR5LeNNTxamz_Z101255320002Rev.00.pdf)**: A 32-bit processor designed for advanced driver-assistance systems (ADAS) and other demanding safety-critical applications.

**[E6-AS](https://sifive.cdn.prismic.io/sifive/Zp9ptR5LeNNTxam0_Z101255320003Rev.00.pdf)**: A 32-bit processor supporting split-lock functionality and targeting ASIL D integrity level in lock-mode. 

**[S7-AD](https://sifive.cdn.prismic.io/sifive/Zp9pth5LeNNTxam1_Z101255320004Rev.00.pdf)**: A 64-bit processor optimized for safety-critical functions that delivers exceptional performance for zonal controllers and other complex automotive systems.


**What are the benefits for SiFive’s customers?**

By meeting strict cybersecurity requirements, our solutions help to reduce the risk of cyber threats, vulnerabilities and recalls, liabilities, and safety hazards. SiFive’s pre-certified IP allows our customers and their customers to achieve compliance with stringent automotive cybersecurity standards and which in turn will help OEMs to meet regulations across the globe, including the UNECE WP.29 R155. This certification helps to accelerate the development cycle and get products to market faster. To further streamline the design process, SiFive provides our customers with a security package, which includes a comprehensive security manual and a detailed cybersecurity capability and interface report. 

**How does industry collaboration play a role in automotive security?**

Tackling cybersecurity threats is extremely complex, so collaboration across the supply chain is critical. SiFive collaborates with the automotive industry through various forums e.g. Auto-ISAC, which brings together OEMs, Tier-1, Tier-2 suppliers, and other providers to align on automotive cybersecurity threats, attacks, and protective measures. By working together, we can all work to better understand the current threat landscape, anticipate future issues, and mitigate potential threats. SiFive is also actively involved in RISC-V International’s Automotive special interest group (SIG) to accelerate the adoption of RISC-V for the automotive industry.

**Why is automotive cybersecurity especially challenging today?**

As vehicles become more connected and reliant on software, the attack surface expands. There are many real-world examples of vulnerabilities that have been exploited to remotely control vehicles, steal data, and disrupt critical systems. The consequences of these exploits could seriously jeopardize the safety of passengers, not to mention the privacy and financial risks of having users’ data compromised. 

It’s also important to remember that SDVs often reuse the same software and hardware already developed for other applications beyond automotive, which helps to minimize the costs of developing automotive-specific solutions. The downside is the same exploitation techniques that exist for other applications can be reused for vehicles. Additionally, there are many different ways that cyberattacks on vehicles can be executed, including through memory safety systems, a lack of isolation, code injection, or through specific vulnerabilities (e.g. a lack of security on a CAN bus). Tier-1 and Tier-2 suppliers, along with the rest of the supply chain, need to ensure that there are not any security holes in any component used in a vehicle—a vulnerability anywhere in the system comprises the entire vehicle. 

**What’s next for SiFive?**

SiFive is deeply committed to cybersecurity, so we are working to implement the security practices and guidelines outlined by ISO/SAE 21434:2021 across the other products in our portfolio, as appropriate. 

Our customers know that they can rely on us as their trusted partner to navigate the complex landscape of cybersecurity and offer a head start in building secure and reliable automotive systems. Together, we can create a future where vehicles are not only intelligent and connected, but are also safe and secure from cyber threats.

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SiFive Becomes First IP Supplier to Achieve Automotive ISO/SAE 21434:2021 Product Certification

We are proud to celebrate SiFive’s Priyanka Viswanathan, director of functional safety and cybersecurity, and Monia Chiavacci, senior principal architect of functional safety, for their recognition in Electronics Weekly’s 2024 Women Leaders in Electronics Awards. The program honors women who have made significant technical achievements and have had a positive impact on the electronics industry. Priyanka brought home an award in the Safety and Compliance category, and was recognized as a finalist in the Unsung Hero in Leadership Role category. Monia was a finalist in the Innovator of the Year category.

“Congratulations to Priyanka, Monia, and all of the other innovators who were recognized by Electronics Weekly for their contributions driving the silicon industry forward,” said Patrick Little, chairman, president, and CEO of SiFive. “Both Priyanka and Monia have been instrumental in building out the capabilities of SiFive’s automotive portfolio, which has already seen strong customer demand across the globe.”

Priyanka’s recent achievements include leading the charge on SiFive’s new ISO/SAE 21434 certification for the automotive sector. As cars are becoming smarter, it’s pivotal that automakers safeguard users’ data and other sensitive information about vehicles. By achieving ISO/SAE 21434 compliance certification, SiFive is making it easier for automakers to meet the latest security requirements in their designs. Plus, we’re bringing the security practices and guidelines outlined by ISO/SAE 21434 to other markets as well. Thanks to the work of Priyanka and her team, we’re raising the bar for security across the RISC-V ecosystem.

 ![Awards recipients](https://images.prismic.io/sifive/ZkOOkiol0Zci9HzX_20240423_215709.jpg?auto=compress,format)

Monia has also been integral to the success of our automotive portfolio, helping SiFive bring to market three automotive products as part of the first phase of our long-term roadmap and portfolio. As part of this process, Monia established the Road Vehicle Functional Safety (FuSa) methodology from scratch for RISC-V IP. She also guided the incorporation of new technologies, such as new variants of core lockstep, aggressive error protection within uncore IP, and the formulation of FMEDA (Fault Mode Effects and Diagnostic Analysis) documents for customers. 

SiFive’s automotive portfolio—which includes the SiFive Automotive™ E6-A, X280-A, and S7-A—address critical needs for current and future applications in the automotive market, including infotainment, cockpit, connectivity, ADAS, and electrification. These products offer industry-leading performance, with the lowest area and power consumption, and are being tailored to vehicle-specific needs for safety, security, and performance.
Congratulations again to Priyanka and Monia for this prestigious recognition and their efforts in making SiFive the leader of RISC-V computing. 


SiFive Leaders Recognized by the 2024 Electronics Weekly Women Leaders in Electronics Awards


 
SiFive was busy in Washington, D.C. this week, participating in a number of exciting meetings surrounding the historic visit of Japanese Prime Minister Kishida to the United States. The visit highlights the strength of cooperation between the two countries and the importance that the semiconductor industry holds in this alliance. SiFive was honored to occupy a seat at the table alongside industry powerhouses and key government officials from both nations.
 
Jonathan Gentin of SiFive joined a U.S.-Japan Semiconductor Suppliers roundtable and explained to participants how RISC-V and SiFive’s collaborative ecosystem is well poised to enhance innovation and cooperation between the U.S. and Japan. RISC-V, of course, is an open standard that allows for collaboration in all emerging areas of compute ranging from AI to automotive to datacenter and to consumer devices.  As the leader in RISC-V, SiFive is working with lead partners to continue to grow RISC-V in Japan.
 ![US Commerce Secretary Raimondo with the Roundtable](https://images.prismic.io/sifive/f61b14d9-bd26-4cd6-9fad-a2b0e22049da_US+JP+Supplier+Event+Photo+Sec+Raimondo+1.jpg?auto=compress,format)




SiFive was honored to join the roundtable (photo above) which included U.S. Secretary of Commerce Gina Raimondo; Tarun Chhabra, Special Assistant to the President and Senior Director for Technology and National Security; Hosaka Shin, Vice Minister for International Affairs, Japan’s Ministry of Economy, Trade and Industry (METI); Nohara Satoshi, Director-General, Commerce and Information Policy Bureau, METI; and representatives from a select group of U.S. and Japanese semiconductor companies. 
 ![Group with Senator Schumer](https://images.prismic.io/sifive/a5f7ec10-df39-4fc1-86ab-cf3eebff1554_US+JP+Group+Photo+Sen+Schumer-2.JPG?auto=compress,format)
 
After the roundtable a smaller group (including SiFive) met with United States Senator and Majority Leader Chuck Schumer on Capitol Hill. Senator Schumer, who was instrumental in spearheading the CHIPS Act and like Secretary Raimondo has long championed the semiconductor industry as vital to U.S. interests, highlighted the critical role semiconductors have played in cultivating the strength of the U.S.-Japan alliance, opportunities for broad cooperation between the United States and Japan in research and development, and the domestic success of the CHIPS Act (including in New York). 
 
 

Japan and the United States have a long history of cooperation in semiconductor equipment, software and hardware.  SiFive is involved with METI and working with others to help spur new innovation in Japan based around RISC-V. Japan has a wealth of highly talented engineers, a sophisticated legal system that protects intellectual property rights, and a favorable business environment that encourages companies like SiFive to partner with the leading companies and innovators in Japan.  
 
“SiFive has strong business momentum in Japan and we work closely with many of its technology leaders in AI, automotive and consumer electronics. We were honored to join the U.S.-Japan roundtable in Washington, D.C. and showcase our cooperation and innovation,” said Sam Rogan, President and GM, SiFive Japan.
 
**Innovation leadership and job creation in the United States**
 
Tom Leahy SiFive head of Aerospace and Business Development was also in the Capitol with members of an SIA (Semiconductor Industry Association) delegation who visited with several members of Congress and staffers to discuss a variety of issues including the importance of RISC-V to the future of the semiconductor industry, the broader importance of the CHIPS Act, and the investment required to ensure that innovation leadership continues in areas such as AI and Compute. 

 ![SIA meeting with Senator Mark Kelly](https://images.prismic.io/sifive/b57cdbe5-aea7-4e99-aee3-a8a2dc3fbeb4_IMG_0813.jpg?auto=compress,format)


“RISC-V was invented in the United States and SiFive was founded here in Silicon Valley by the RISC-V inventors,” said Leahy. “We appreciated the chance to sit down with leaders and policy makers in Washington to explain the strategic value of semiconductors in terms of spurring innovation, job creation and domestic chip capabilities. I was pleased to also explain why our technology is being used by Government agencies like NASA to provide future critical computing needs.” 

 

RISC-V has clear benefits for Aerospace and Defense applications and SiFive is working with a number of companies and government agencies to bring its proven flexible, energy efficient powerful compute to a wide variety of applications. 
 





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SiFive in Washington: Japan partnership and a stronger semiconductor ecosystem

In the first of what we expect will be a number of webinars this year, Krste Asanovic, SiFive co-Founder, Chief Architect and RISC-V innovator, sat down to talk about how SiFive is solving real-world AI challenges and some of the applications where RISC-V is gaining rapid momentum. He also discussed how our latest innovations in high performance RISC-V computing are bringing exciting open standard solutions to AI and ML workloads. 
 
You can watch the webinar here:

[Creating Agile AI Systems with Open RISC-V Solutions](https://www.sifive.com/resources/webinar/creating-agile-ai-systems-with-open-risc-v-solutions)

We’ve also made his slides available for download.


creating-agile-ai-systems-open-risc-v-solutions.png

New Webinar on Creating Agile AI Systems with Open RISC-V Solutions

Securing your vehicle used to mean remembering to lock your doors at night and hiding your belongings under the seat when parked in public lots. Now that today’s smart cars are running hundreds of millions of lines of code, vehicle security has become much more complicated. To protect private data and sensitive information in vehicles, it’s critical that automotive processors support the latest functional safety and cybersecurity standards.

SiFive has always been at the cutting-edge of vehicle safety, and we recently hit a new milestone by achieving [ISO/SAE 21434](https://database.ul.com/certs/ULCAP_P110.pdf) compliance. ISO/SAE 21434 is the first automotive-focused standard specifying a cybersecurity framework for next-generation software defined vehicles (SDVs). Our RISC-V automotive products already offer unparalleled design freedom and flexibility for the automotive market, and now our customers can design vehicle components with the confidence that our solutions meet the most demanding security requirements.

Let’s dive in further to explain why ISO/SAE 21434 is so important. The standard provides specific requirements for cybersecurity processes and establishes a common language for communicating and managing cybersecurity risk across the supply chain—protecting original equipment manufacturers (OEMs) and end users from cybersecurity threats. ISO/SAE 21434 certification is seen as a prerequisite for OEMs in selecting their suppliers, as this certification allows OEMs to meet the requirements for UN R155, a regulatory framework designed to ensure that vehicles are secure.

Many of the processes required by the ISO/SAE 21434 are not new for SiFive. SiFive expanded on its existing processes to meet additional requirements specified by ISO/SAE 21434, including providing its customers with a security package that includes a security manual, and a cybersecurity capability and interface report. Now all of SiFive’s automotive products include this package to streamline the standardization process at every level of the supply chain.

With SiFive’s deep commitment to quality, security, and safety, our efforts don’t stop here. SiFive will be implementing the security practices and guidelines outlined by ISO/SAE 21434 as appropriate across the other products in our portfolio. This will make it easier for our customers across different verticals to take advantage of the latest security capabilities, even if certain segments do not have as strict security requirements as the automotive market. 

To learn more about SiFive Automotive™ solutions, please [visit](https://www.sifive.com/cores/automotive). 




SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 Certification

**In stock today!** 

We have had a lot of requests for HiFive Unmatched Boards since the first model sold out, and to meet this immediate demand we are making another 1000 available to you through our distribution partner, Mouser Electronics.  These boards are liable to go quickly, so if you’re looking for a flexible development platform to try out your new RISC-V designs place your order soon.

The updated [Revision B boards](https://www.sifive.com/boards/hifive-unmatched-revb) are completely software compatible with the originals, and are powered by the SiFive Freedom U740 (FU740), an SoC that includes a high-performance multi-core, 64-bit dual-issue, superscalar RISC-V processor (Quad SiFive Essential™ U74-MC) with 16GB of DDR4, Gigabit Ethernet, PCIe expansion, USB 3, and M.2 sockets for Wi-Fi, Bluetooth and NVMe storage. The complex is accompanied by a single SiFive Essential S71 monitor core available for real time applications. 

The updated HiFive Unmatched Rev. B boards are available through our partner Mouser under Mouser part #115-HF105-001 [here](https://www.mouser.com/ProductDetail/SiFive/HF105-001?qs=Imq1NPwxi75JBw6ulD0quQ%3D%3D) and are ready for fulfillment from the warehouse in a couple of weeks from the time an order is placed. 

More information on the [HiFive Unmatched Rev. B](https://www.sifive.com/boards/hifive-unmatched-revb) can be found on our Boards landing pages [here](https://www.sifive.com/boards). 


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Unlock the Possibilities with HiFive Unmatched RISC-V Development Boards 

We’d like to thank our moms, the Academy and …well ok, maybe it’s not the Oscars but the 2023 RISC-V Summit was filled with innovation, collaboration, and a SiFive award for one of our most popular products! The SiFive Performance P470 RISC-V processor was awarded [Embedded Computing Design’s Best in Show Award](https://embeddedcomputing.com/technology/processing/semiconductor-ip/risc-v-summit-north-america-2023-best-in-show-nominees) at this year’s event. Winning in the microelectronics, microprocessors and IP category, the SiFive Performance P470 brings unparalleled compute performance and efficiency to small size, high volume applications such as wearables, smart home devices, and consumer devices.  At the Summit Samsung representatives spoke about their experience working with the P470 in silicon and also provided some great overall advice to the RISC-V ecosystem.  

The SiFive Performance P470 is the company’s first efficiency-focused, Out-of-Order, area-optimized vector processor. It is significantly smaller than competing solutions and is optimized to have best-in-class performance efficiency and area density. The P470 delivers significant upgrade opportunities over legacy processors, offering impressive compute density, power efficiency, and robust feature sets to handle the most demanding workloads and bring significant cost savings to customers. Plus, the processor offers greater design flexibility to meet specific application needs, power budgets, and cost envelopes.

 ![Award on deisplay in the SiFive booth in the Developer Zone at the RISC-V Summit](https://images.prismic.io/sifive/fa15cb2b-31a4-44e4-918f-42cc45bd7694_IMG_4866.jpg?auto=compress,format) 

Learn more about the award-winning processor and the rest of SiFive’s Performance family [here](https://www.sifive.com/cores/performance-p450-470). 

Congratulations to all of the other Best in Show Award winners and nominees. Together the RISC-V ecosystem is proving that the future of RISC-V has no limits!



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SiFive’s Performance P470 Receives Best in Show Award at the RISC-V Summit

The progress RISC-V has made in the past few years is amazing. The leap from being an ISA deployed for basic embedded cores to powering high performance applications in consumer products, datacenters, autonomous vehicles, and next generation wearables, has come faster and stronger than anyone anticipated. The RISC-V community has grown from a few dozen contributors to more than 3,900 members – spanning markets, applications, and geographies. The ISA has become foundational technology for the entire semiconductor industry, and we are now witnessing the beginning of a profound shift toward RISC-V. Some of the world’s largest and most influential technology companies have joined our ranks and further strengthened our ecosystem, a community which, over time, will rival all others. Qualcomm and Google’s recent announcement of their collaboration on a RISC-V based wearables platform that will power next generation Wear OS solutions is a groundbreaking milestone that will pave the way for more RISC-V products within the ecosystem. This further highlights the relevance and momentum of RISC-V’s unstoppable march. 

RISC–V is clearly real, growing rapidly and here to stay! 

At SiFive, we are urgently re-inventing computing. We have been driving the RISC-V transformation since its inception and our products are being integrated by the most talented designers, in the most innovative products, across the global semiconductor industry. 

Smart, fast-growing businesses regularly pause to take a hard look at their priorities to ensure their strategies, workflows, capabilities, and people are fully aligned. After years of rapid growth, we looked at SiFive’s business and saw the need to realign our operations with the forward-looking objectives of the company. While preserving our nimbleness and close collaboration with customers, we identified a need to refocus our priorities and our resources on the most promising opportunities. 

The resulting restructuring has created a lot of discussion and some misplaced speculation amongst the RISC‑V and semiconductor communities. I feel it is important to share our rationale with you. 

SiFive today is in tremendous shape. We are deliberately building a company that can and will outperform in any environment – and in the long run. We are very well funded for years to come, with engaged, highly supportive investors, and we are realizing revenues and compounding royalties from many of the world’s leading semiconductor companies. We continue to heavily invest in advanced R&D to extend our technological leadership, while also working to accelerate the delivery and support of industry-leading products that exceed our customers’ expectations. 

We take immense pride in our open culture and talented employees. Undertaking the reorganization involved difficult decisions, yet strategically, I believe it was required for us to grow and continue to lead our industry forward. We wish all our colleagues well. 

SiFive continues to deliver the broadest and highest performing <a href="https://www.sifive.com/risc-v-core-ip">portfolio of RISC‑V products</a> in the world. Our IP has been integrated into countless products and is shipping in high-volume silicon today. We continue to add to our list of industry firsts, and to our portfolio, including the products we announced earlier this month – the <a href="https://www.sifive.com/cores/performance-p870-p870a">SiFive Performance P870</a> and <a href="https://www.sifive.com/cores/intelligence-x390">SiFive Intelligence X390</a>. 

Our four product-family commitment remains unchanged, with Essential, Intelligence, Performance, and Automotive solutions. With these product lines we are well positioned to drive growth and take advantage of the biggest opportunities of this era: AI, ADAS, Electric Vehicles, Wearables, Mobile, and more. We have exciting new opportunities in AI applications – and with consumer products like wearables and mobile as Google brings Android to the RISC-V ecosystem. In automotive, we are increasingly being selected for the cars of the future. Our broad portfolio lets customers meet their product goals whether designing an embedded device or looking to do generative AI in the datacenter– where our solutions all share the common RISC-V software ecosystem. 

Every industry is focused on implementing AI and we are capturing new growth as the shift to AI accelerates a new era of high-performance computing. As a result, the semiconductor industry benefits more than ever from RISC-V. AI applications come down to a combination of high-performance general-purpose compute and programmable specialized accelerators with extreme performance. The challenge is the need for improved power efficiency and compute density (in addition to programmability and flexibility), and that’s why RISC-V is fast becoming the ecosystem of choice. With AI integrated into everything, RISC-V is becoming a critical ingredient. Today in AI there is excitement about transformers, but what will tomorrow bring? The flexibility of SiFive’s solutions allows customers to respond to these continuous changes. 

We have adapted our organization to strengthen our agility and capture emerging growth opportunities, more deeply partner with our industry leading customers, accelerate the execution of our advanced roadmaps, and continue to extend our position as the global RISC-V leader. 

SiFive’s growth has never been stronger, our opportunities have never been better – and I have never been more confident that SiFive will revolutionize computing, with RISC-V, in ways we have not yet begun to imagine. 

Keep moving forward! 

Patrick

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SiFive congratulates Arm on its IPO, which represents a momentous step forward for the entire semiconductor ecosystem. This IPO has brought more awareness to the public about the critical role of computing architectures, specifically the instruction set architecture (ISA), and the need for high-quality, high-performance processor IP to drive our industry forward. Competition is essential for a healthy semiconductor industry, and we continue to hear from companies about the importance of having choice in the processor market, especially after the chip supply challenges of the last few years. Arm has helped focus a spotlight on the ISA and CPU IP, and is highlighting its criticality to the fastest growing areas of semiconductors, areas like datacenter and AI, automotive, consumer, and mobile. 

Part of the excitement has been a new recognition of how big the market opportunities are, and there is room for all of us. These markets need rapid innovation and customization, which are consistent themes in our conversations with customers. It’s no secret that SiFive’s founders developed RISC-V as a response to the limited customization options of closed, proprietary architectures. We work with global technology leaders and SiFive’s high-performance IP is being designed into everything from aerospace applications to automotive, the datacenter, wearables, and beyond. While the semiconductor landscape has evolved considerably since then, what hasn’t changed is that companies want design flexibility and freedom: SiFive and RISC-V make that possible. After all, there are no limits with RISC-V.


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Arm IPO Underscores the Ongoing Compute Supercycle 

SiFive recently received its official ASIL-B Ready Functional Safety Certificate from the SGS-TUV organization, and to understand the implications, I discussed this achievement with SiFive’s industry recognized Automotive Functional Safety experts, Priyanka Thachakuzhiyil Viswanathan, Director Functional Safety and Cybersecurity, and Monia Chiavacci, Sr. Principal Architect, Functional Safety. This is a great step forward for our customers. Here’s what I learned. 

In September 2022, we announced the SiFive Automotive™ E6-A, X280-A, and S7-A solutions to address the critical needs for current and future applications like infotainment, cockpit, connectivity, ADAS, and electrification, as the market transitions to zonal architectures and manufacturers require the energy efficiency, simplicity, security, and software flexibility that RISC-V offers. We partnered with TUV SGS in parallel to begin the first in a series of confirmation measures (confirmation measures include confirmations reviews, functional safety audit and FuSa assessment) for this product line. 

We are pleased to have achieved the first milestone, with TuV SGS ASIL -B Ready certification, for the SiFive E6-AB IP core from this automotive series product line. This is a confirmation that SiFive E6-AB Core Complex’s safety architecture can meet the hardware architectural metrics (SPFM and LFM) requirements for ASIL B. For mere mortals, such as myself, these refer to the Single Point Failure Metric and the Latent Fault Metric, which are relative hardware architectural metrics specified by ISO 26262 to quantify the effectiveness of a design against random hardware faults.

This means we have evidenced to TuV SGS, via our safety manual and safety analysis report (using the Failure Modes Effects and Diagnostic Analysis (FMEDA) and Dependent Failure Analysis (DFA)), that E6-AB Core Complex can meet the SPFM target >= 90% and LFM target>= 60%. This is a great demonstration of our automotive technical capability and strong commitment to customers requiring functional safety standards conformance, ensuring as a first step, that our IP technology is designed with a “Safety Architecture” that will address their functional safety needs in that foundational technology. Best of all, this certification was achieved solely based on the IP’s hardware safety mechanisms, meaning no software test library (STL) creation or integration is required for this part of an overall system certification.

This also prepares us for the next step, the functional safety assessment with TUV SUD, building upon this earlier foundation. This will include the following: <li> ASIL D systematic capability (Process) assessment for E6-AB, as well as the other variants in the family designed specifically with ASIL-D features, E6-AD and E6-AS
<li> ASIL B diagnostic capability assessment for E6-AB as part of FuSa assessment on top of already existing ASIL B ready certificate
<li> ASIL D diagnostic capability assessment for E6-AD and E6-AS in lock mode.


To be clear, this will add the assurances that the entire SiFive development process and the life cycle of our products conforms to the requirements for ASIL D, which is of the highest rigour possible as suggested by ISO 26262 for the design and development of products. From marketing requirements to RTL implementation and delivery, including customer support, errata management and product end-of-life policies and procedures, these robust processes ensure quality, and becomes a part of our ability to design, deliver and support our IP technology for our customers. 

With significant design wins with key automotive vendors, SiFive has strong momentum in automotive and this plan demonstrates to our customers that our products are developed to more stringent design and development processes than even those targeted for ASIL B applications. Our strong team of functional safety experts is working closely with our automotive cores design team to create exciting new automotive solutions. Customers can incorporate our products in applications requiring these specific higher integrity levels with confidence. 

For more information about our Automotive Solutions family of products, please visit our automotive [web pages](https://www.sifive.com/cores/automotive) or to talk to us about your specific challenges [contact sales](https://www.sifive.com/contact-sales).

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ASIL B Ready Certification for SiFive Automotive Solutions


**Bob Monkman (SiFive), with Bill Lamie (PX5) and Rafael Taubinger (IAR)**

I recently had a great conversation with Bill Lamie, President/CEO of PX5,  and Rafael Taubinger, Sr. Product Marketing Manager at IAR, regarding the recent port of the industrial-grade PX5 RTOS to the SiFive HiFive Rev B RISC-V development board (powered by a 32-bit SiFive RISC-V embedded microcontroller), using the IAR Embedded Workbench tools suite. I wanted to understand why Bill, who has been a serial innovator in embedded for decades, chose SiFive and IAR as the platform and development solutions, respectively, for his most recent venture. And, since I wasn’t yet familiar with the PX5 RTOS, I wanted to gain some insights into this latest technology. 
As a veteran of the RTOS market myself, I was super impressed that PX5 can be configured for minimal size, requiring less than 1KB of Flash and 1KB of RAM on 32-bit microcontrollers. The kernel features native POSIX threads API, making it portable and familiar to developers across the spectrum. The PX5 team has a particular focus on extensive validation and verification to enable use in safety-critical applications that require documented safety practices. 

This was a big reason they used the ubiquitous IAR Embedded Workbench tools as well. The IAR solutions have been around for 40 years and have been used in countless safety-critical use cases with worldwide customers. The available functional safety edition is certified by TÜV SÜD and complies with the requirements of ISO 26262, IEC 61508, IEC 62304 and many more standards. IAR has a complete development toolchain with a highly optimizing compiler, and a great debugger that has been one of Bill’s favorite debuggers for the 20+ years he has been working with the IAR team. He told us that he recently used IAR’s code coverage analysis tools to ensure 100% code coverage in his own test framework for the PX5 RTOS, and the code analysis tool IAR C-STAT to meet MISRA and other coding standards established to deliver demonstrably high-quality code to the market.

Like a fast growing number of software vendors in the market today, both PX5 and IAR recognize that the RISC-V open ISA standard is gaining tremendous momentum, and they’re intent on delivering verified commercial support for RISC-V to their customers as the inevitable demand grows. I asked Bill why he chose SiFive as a RISC-V go-to-market partner, and the answer there was also consistent with what we hear every day from the ecosystem. 
PX5 sees SiFive as a leading RISC-V IP provider by multiple measures. They appreciate that SiFive’s founders are the same team who invented the RISC-V Instruction Set Architecture (ISA) in 2010, and that SiFive is a key thought leader and innovator in the evolution of RISC-V ISA in the overall ecosystem. SiFive is addressing a broad swath of market segments, including the safety-critical applications that PX5 is seeking to be ready to address. SIFive supports a single, consistent instruction set across all of our product offerings, increasing portability, while reducing costs and maximizing the energy efficiency, simplicity, security, and flexibility upsides that RISC-V offers.

This all makes great sense, and we at SiFive appreciate the enthusiasm and trust of software partners like PX5 and IAR, who are working together with us to deliver terrific value to the market.
 
For a free evaluation of the Px5 RTOS on the SiFive HiFive1 RevB board, please [visit](https://px5rtos.com/free-rtos-download-evaluations) and scroll down to the SiFive section. 

More information about PX5 RTOS is available [here](https://px5rtos.com/). 
For more information on IAR solutions for RISC-V, please [visit](https://www.iar.com/products/architectures/risc-v/). 



Expanding the RISC-V Ecosystem, with PX5, IAR and SiFive

You are invited to attend an upcoming [webinar](https://www.eventbrite.com/e/silicon-catalyst-webinar-sifive-maximizes-compute-density-with-its-risc-v-tickets-629304716347?utm_campaign=industry&utm_medium=social-organic&utm_source=linkedin&utm_content=field_high-tech_Silicon-Catalyst-Webinar_1-few_webinar-3rd-party_register_na_en_us&campaignID=7015w000001Cok2AAC&utm_term=silicon-catalyst-webinar) where Ansys will talking with SiFive's Phil Dworsky to discuss the pursuit of maximum compute density in our RISC-V processor cores. 

The presentation will cover topics such as managing dynamic power throughout the design process and creating efficient power distribution networks that meet voltage drop requirements. By attending, you will gain valuable insights into design flows that can help you achieve these objectives in your own projects. 

Don't miss out on this exciting opportunity to learn from industry experts and stay ahead of the curve. Register now to secure your spot.

You can register [HERE](https://www.eventbrite.com/e/silicon-catalyst-webinar-sifive-maximizes-compute-density-with-its-risc-v-tickets-629304716347?utm_campaign=industry&utm_medium=social-organic&utm_source=linkedin&utm_content=field_high-tech_Silicon-Catalyst-Webinar_1-few_webinar-3rd-party_register_na_en_us&campaignID=7015w000001Cok2AAC&utm_term=silicon-catalyst-webinar)


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Ansys Joint Webinar: SiFive Maximizes Compute Density With Its RISC-V Processor Cores

In March, SiFive announced the opening of its new office in the greater Boston area. 2022 was a monumental year for SiFive and 2023 is shaping up to be another strong year. Marlborough was an ideal location for the new office as the company continues to expand its footprint and serve our growing customer base located in Massachusetts and the surrounding Northeast region. 

The office will be led by Shubu Mukherjee, vice president of architecture at SiFive, with plans to grow its headcount in the next 12-to-24 months. The greater Boston area is rich in talent in all areas of semiconductor development, including architecture, RTL, digital verification, and physical design, as well as sales, marketing, and business development. Having a physical presence in the area will help reach both experienced professionals as well as tap into the strong University programs in the region.

 ![SiFive Boston team members celebrate opening](https://images.prismic.io/sifive/d325b28f-01dc-4270-bb0a-4464b7fe5938_img_0665.jpeg?auto=compress,format) 
SiFive is always seeking talented designers and engineers ready to make an impact on the world and help accelerate the adoption of RISC-V. You can always check our website for open roles. [Careers](https://www.sifive.com/careers) 


SiFive Expands U.S. Presence with New Office in Boston

As the inventors of RISC-V and performance density leaders, SiFive is committed to spreading the word about how this groundbreaking open architecture is reshaping the computing industry and ushering in new possibilities. Last week, we hosted the [SiFive Tech Forum in Hsinchu](https://www.youtube.com/watch?v=o8jrPQQvzGw), the technology heart of Taiwan, to bring together hardware engineers, developers, and other technology leaders to talk about the incredible momentum of RISC-V to-date and how SiFive is leading the RISC-V revolution. The event was well over subscribed, which highlighted the eagerness with which the attendees were keen to learn about the latest SiFive solutions. Read on to find out more about what we covered during the SiFive Tech Forum.  And you can view the presentations [here](https://www.youtube.com/@sifiveInc)

 ![Taiwan event](https://images.prismic.io/sifive/fc2afe63-cd62-4fa0-8654-7bfedee7ebee_IMG_4425.jpg?auto=compress,format)

 
Jack Kang, SVP, Business Development, Customer Experience, and Corporate Marketing kicked things off by talking about the RISC-V Revolution and emphasizing how RISC-V is inevitable and has no limits, and highlighted SiFive leadership in driving RISC-V into every technology market. There are billions of RISC-V cores in the market and the demand for the flexibility and freedom that RISC-V enables is growing stronger every day. SiFive’s RISC-V portfolio has already been adopted for a wide variety of markets – from aerospace to automotive to consumer devices, and the datacenter – and we’re rapidly expanding our global footprint as we work with the biggest and best technology companies across APAC, Europe, North America, and beyond. 


![A packed house](https://images.prismic.io/sifive/b9a70681-7f50-4d7f-853b-ed2e2d1d28ab_IMG_4399.jpg?auto=compress,format)

Our team then dove into the impressive compute performance and efficiency of SiFive’s new P600 and P400 series of RISC-V processors, which are perfectly tuned to offer the best power and performance efficiency and compute density for next generation wearables, the smart home, industrial automation, and other consumer devices. 

Another area we addressed is how SiFive is accelerating AI/ML innovation with our SiFive Intelligence solution. SiFive Intelligence is a high-performance AI dataflow processor with scalable vector compute resources to meet the complex processing and data management requirements of AI/ML applications, from extremely low power to high-performance compute. 

Of course, we also had to talk about automotive, a huge growth opportunity for SiFive and RISC-V. As the automotive market transitions to zonal architectures, manufacturers see significant benefits in the energy efficiency, simplicity, security, and software flexibility that RISC-V offers all within a single Instruction Set Architecture (ISA). SiFive offers the broadest range of high-end automotive applications and real-time automotive processors, offering industry-leading performance, with the lowest area and power consumption, and tailored to vehicle specific needs for safety, security, and performance. 

To finish off the day, we shared an update on the latest RISC-V tools, software, and development boards. We’re especially excited about the upcoming HiFive Pro P550 Development System (previously code-named Horse Creek) that we’re unveiling in partnership with Intel this summer. This high performance platform features a quad-core SiFive Performance™ P550 processor and is implemented in the Intel 4 technology platform. We also showcased how the RISC-V partner ecosystem is delivering the comprehensive range of solutions including compiler tool chains, integrated open application environments, advanced debug and trace solutions, application protocol middleware, real-time operating systems, and FPGA kits to meet the needs of the market now and in the future.  

We’d like to thank everyone who attended the SiFive Tech Forum, and our team’s hard work in making it a success!



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Unleashing the Potential of RISC-V: A Recap of the SiFive Tech Forum

SiFive is in attending 2023’s embedded world from March 14-16, and we’d love to see you there! Meet us in Nürnberg to learn about some of our recent announcements, including our new processors for wearables. These new processors, the P670 and P470, offer unrivaled choice and flexibility with the perfect balance of performance and efficiency. The P670 is ideal for applications like premium wearables, networking, robotics, and mobile. Meanwhile, the P470 – SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor – is designed for applications like wearables, consumer, and smart home devices.

In case you missed it, we also recently introduced new automotive processors. SiFive’s Automotive X280-A, E6-A, and S7-A solutions address critical needs for current and future automotive applications like infotainment, cockpit, connectivity, ADAS, and electrification. The X280-A (the automotive version of SiFive’s X280 vector processor) has industry-leading performance to meet the complex computing requirements of sensor fusion and ML intensive workloads. The E6-A series is designed for real-time, 32-bit applications including system control, hardware security modules (HSMs), and safety islands, and also serves as a standalone solution for microcontrollers. Additionally, the S7-A is a 64-bit, high-performance real-time core optimized for the needs of modern SoCs with performant safety islands. 

Let us know if you’d like to set up a meeting to learn more about these new products and how the open era of computing is transforming the semiconductor industry. SiFive saw record growth in 2022 driven by global demand for RISC-V and a growing awareness of it's compute density and power efficiency advantages.  We work closely with more than 100 leading customers in applications including automotive, AR/VR, client computing, datacenter, and the intelligent edge. To set up a meeting, please contact sifive@racepointglobal.com.   



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At the 2022 RISC-V Summit, SiFive highlighted collaborations with some of the world’s biggest companies in our 10+ talks on stage and with our demos. SiFive also gave an exclusive first look at an upcoming product, and three of our employees won awards.

One highlight was the keynote from SiFive’s CEO, Patrick Little: [“RISC-V Spotlight: RISC-V Everyone Wins”](https://www.youtube.com/watch?v=VxG87XLKPvM). Patrick highlighted how the momentum and excitement for RISC-V is growing and how today it is in billions of cores on the market and is being designed into a huge range of applications. Patrick covered the early vision for RISC-V and emphasized the importance of collaborating to build a strong community and ecosystem for RISC-V.

As part of our efforts to build out the RISC-V ecosystem, SiFive has partnered with Intel to develop the HiFive Pro P550 Development System (previously code-named Horse Creek). During his keynote, Patrick was joined on stage by Intel Foundry Services’ Bob Brennan to share a first look at this high performance platform that features a quad-core SiFive Performance™ P550 processor and is implemented in the Intel 4 technology platform. The board will enable a new generation of RISC-V software, continuing the tradition of SiFive HiFive boards that have helped drive the growth of the RISC-V ecosystem. The board will be commercially available in the summer of 2023. 

SiFive ecosystem partners and customers, including Ashling, AWS, Canonical Ubuntu, Codeplay, Google, Imperas, Intel, Lauterbach, Microchip, Qualcomm, Rice University, Solid Sands, Synopsys, and Tenstorrent, were featured throughout the event and in a panel session entitled [“It takes a village… to build an ecosystem,”](https://www.youtube.com/watch?v=kwQni8zo5w0) which reviewed the strong state of the RISC-V ecosystem as well as the next steps that key contributors are leading.

SiFive’s additional presentations throughout the event focused on our collaborations and partnerships to bring our high-performance RISC-V portfolio to automotive, [aerospace](https://www.youtube.com/watch?v=GrTjDgSpSmY), and beyond. For example, through our partnership with Microchip, SiFive is a part of NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor, which delivers a 100x increase in computational capability to help propel next-generation planetary and surface missions. Jack Kang, SVP, Biz Dev, CX, Corp Marketing at SiFive, [summed up](https://www.youtube.com/watch?v=Fa3FJhhmrHc) why so many companies are choosing RISC-V and SiFive: “RISC-V products are just better. Better power, better performance, and more.” 

Jack also took some time to chat with RISC-V International’s CEO Calista Redmond about our momentum to-date and what’s ahead. 

SiFive continues to invest strongly in the RISC-V community, with many of our employees actively participating in RISC-V International’s technical committees. In recognition of these efforts, three of SiFive’s employees won awards from RISC-V International. Yunsup Lee, SiFive’s Co-Founder & Chief Technology Officer, received a Technical Contributor Award for his work as Chair of the Technical Steering Committee (TSC). Craig Topper, Principal Compiler Engineer, and Kito Cheng, Compiler Engineer, received Software Contributor Awards for their hard work on RISC-V technical committees. Check out the full list of winners [here](https://riscv.org/announcements/2022/12/risc-v-honors-outstanding-technical-and-community-contributions-for-2022/).

You can read more about SiFive’s latest activities and momentum in 2022 [here.](https://www.sifive.com/press/sifive-delivers-record-growth-in-2022-with-fast-growing) To watch SiFive’s presentations at the RISC-V Summit, visit [here](https://www.youtube.com/@RISCVInternational/videos).



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SiFive Makes a Splash at the RISC-V Summit with 10+ Talks, Demos, and a Surprise Product Reveal

SiFive has seen tremendous growth over the past few years with strong year-over-year revenue growth and is in the top 10% of the Inc. 5000 list of private companies. With more than 550 employees around the world, we’re continuing to grow our team and expand our footprint across different regions to meet the strong customer demand for SiFive’s innovative RISC-V IP.

India is one region in particular where we’re focused on building out our team. This month SiFive opened a new design center in Bangalore, India. We have around 90 employees working there currently, and the space has room for around 150 employees as we continue to grow. The Bangalore team is focused on leading edge CPU and platform design, verification, physical implementation and software.  

![SiFive Bangalore team](https://images.prismic.io/sifive/083356ef-c691-4f12-8727-da5b02eb3983_SiFive-BLR-Office.jpg?auto=compress,format) Our Bangalore Team

SiFive also recently opened a new office in Hyderabad, India where the team is working on CPU IP design, verification and software tooling. Additionally, SiFive has a team in Ahmedabad, India working on cutting-edge network-on-chip (NoC) technology.

These recent efforts to expand our presence underscore the massive potential we see in India for silicon innovation. While there is strong momentum for RISC-V all over the globe, the excitement for RISC-V in India is almost unparalleled. This push for RISC-V extends throughout academia, industry, and even the government. The Indian government announced the ambitious [Digital India RISC-V (DIR-V) program](https://pib.gov.in/PressReleasePage.aspx?PRID=1820621) earlier this year to leverage RISC-V to catalyze semiconductor innovation in the country.

We’re hiring in our offices around the world, so we encourage you to apply to work with the best and the brightest as we take high-performance products to the next level.  You’ll get to work alongside the founders of RISC-V as we transform the future of compute and prove that RISC-V has no limits. Learn learn more about our open positions and apply [here](https://www.sifive.com/careers).


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SiFive Expands Presence in India to Keep Up with the Company’s Ultra-fast Growth

 In the fast moving Semiconductor Industry, predictions and papers become obsolete fast and so it’s worth recognizing when a paper has a significant impact on our industry that also has a bit of a timeless nature. The paper, **A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor** (you can read it [here](https://ieeexplore.ieee.org/abstract/document/1253181) was recognized during the award ceremony at MICRO 22 in Chicago October 4th, and we’re proud to share that our very own VP of Architecture, Shubu Mukherjee, (who was at Intel at the time it was written) was there to accept the award on behalf of his fellow authors, Christopher  Weaver, Joel Emer, Steve Reinhardt and Todd Austin.

![Shubu](https://images.prismic.io/sifive/9a5ad323-407b-4eb8-afb9-5cbf0d6b8b47_Slide1.jpeg?auto=compress,format)

The methodology highlighted in the paper has been the foundation for RAS work done by a number of companies over the past 20 years and continues to be used in the FuSa work happening at SiFive and many other companies.
The citation for the award reads:
This paper targets the problem of assessing the cost and reliability trade-offs in a microprocessor.  The authors introduce the concept of Architectural Vulnerability Factor (AVF) which estimates the probability that a fault in a particular hardware structure will result in a user-visible error.  This concept was introduced at a time when continued technology scaling caused the architecture community to stumble upon the "Reliability Wall" and there was significant industry concern about the reliability of computing at scale due to transient faults.  Both industry and academia invested significant efforts to ensure reliable program execution in the presence of such faults. The AVF analysis methodology allowed processor architects to reason about the impact of transient faults early enough in the design cycle to be able to prioritize protection decisions. The paper has had a significant impact on the technical community. At the time of this writing, it has had over 1200 citations on Google Scholar and has received over 40 citations each year for the past 15 years. AVF analysis is now an industry best practice.
 
At SiFive,  Shubu has been instrumental in driving new technologies and his past FuSa work is helping shape our new Automotive Portfolio.
 
Congratulations to Shubu and the other authors.  SiFive continues to attract some of the industry’s best technologists, and we’re proud to showcase their work.  To see our latest opportunities, please see our [careers page](https://www.sifive.com/careers).

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SiFive’s Shubu Mukherjee Recognized Along with Fellow Authors with SIGGMICRO’s Test of Time Award

At the AI Hardware Summit in Santa Clara,  September 14th,  Krste Asanovic, SiFive Co-Founder and Chief Architect, took to the stage with Cliff Young, Google TPU Architect and MLPerf Co-Founder, to reveal how the latest SiFive Intelligence™ X280 processor with the new SiFive Vector Coprocessor Interface Extension (VCIX) is being used as the AI Compute Host to provide flexible programming combined with the Google MXU (systolic matrix multiplier) accelerator in the datacenter. They also talked about why this type of architecture is becoming popular for AI/ML workloads, and how, with this configuration, SiFive provides essential compute capabilities so Google can focus on deep learning SOC development. A video of the talk is expected to be available in early October. 

![Krste and Cliff](https://images.prismic.io/sifive/f25531a2-a8c2-433a-8975-ebee195ec6cc_google+talk.jpg?auto=compress,format)

**SIFive Intelligence X280** 
![SiFive X280](https://images.prismic.io/sifive/772f6782-9114-4d36-aeed-a0592362d008_Slide1.jpeg?auto=compress,format)
The SiFive Intelligence X280 is a multi-core capable RISC-V processor with vector extension, optimized for AI/ML applications in the datacenter. 
As Krste explained, the X280 has a 64-bit applications processor plus an expanded vector unit supporting the RISC-V Vector 1.0 ratified standard, providing a full featured processor designed for vector compute executing standard software. The X280 has 32,  512-bit registers and allows you to gang multiple vector registers together to make a longer vector (up to 8 in a row). This allows operations at up to 4096-bits, which helps reduce power and increase optimizations on cohorts where you have longer vectors. 

SiFive also offers the SiFive Intelligence extensions, which add custom instructions to optimize AI/ML workloads. The X280 runs a full RISC-V software stack as well as a hypervisor. It is a highly efficient, Linux-capable processor  with full applications processor support, supporting up to 48-bit virtual memory space, and private L1 and L2 caches. The vector streams from the L2 cache and all cores share the L3 cache. With the latest X280, SiFive offers improved software compilers for higher performance, a very capable applications core, with a very wide vector unit,  and support for large cache coherent multi-processor configurations.
![Comparison chart](https://images.prismic.io/sifive/a31852c8-13a5-41e0-8c69-739ee9b55f4d_Slide2.jpeg?auto=compress,format)
The chart above shows an example of AI acceleration with Mobilenet, delivering a huge 24x speed up with the X280 standard Vector instructions (vs. the scalar ISA), and then another ~6x acceleration with the SiFive Intelligence extensions. Krste also pointed out that the X280 can run by itself, performing inference tasks at the edge, where it can also act as an apps processor and inference engine for smaller workloads.  

**Game-changing VCIX**
![VCIX overview](https://images.prismic.io/sifive/a79f175a-79c9-4920-8013-77859e16a145_Slide4.jpeg?auto=compress,format)

After the introduction of the X280, SiFive started seeing a lot of customers using it as a companion core. As shown above, the X280 has many features to accelerate AI and ML, but it’s not a massive AI accelerator that is traditionally built for datacenters. Customers building these massive accelerators found they had a bunch of complex compute that needed to be done that their accelerator “really didn’t know how to do.” For example, many found that you need a full featured software stack to run the code that’s not in the kernel that sits on the accelerator. To solve this challenge, customers realized they could put the X280 core next to their large accelerator where it could provide maintenance code and operations code, run kernels that the big accelerator couldn’t do, or provide other valuable extra functions. And the X280 core allowed them to run very fast.   

With this real-world customer feedback, SiFive set out to develop something more ideally suited to this use case. Working with customers like Google, SiFive came up with the Vector Coprocessor Interface eXtension (VCIX), which allows you to plug an accelerator directly into the vector register file of the X280 and communicate on the very fast order of 10 cycles in-and-out. This is helpful for adding complex instructions like color conversions, for example. Overall, VCIX gives you increased performance and much greater data bandwidth, because you go directly into the vector register file, coupled with much lower latency and simplified software. 

VCIX connects to the 32, 512-bit registers in the X280 directly and also to the scalar instruction stream, creating a high bandwidth, low latency path directly coupled to the instruction stream of the X280 scalar processor. Designers can not only offload some functions to the software accelerator, but also have the flexibility of having the X280 handle some functions itself. The benefit, as Krste highlighted, is that you can bring your own coprocessor into the RISC-V ecosystem and get a complete software stack and programming environment. You can run full Linux plus a hypervisor with full virtual memory and cache coherent support.  

**An elegant division of labor with the Google TPU**
![Google TPU](https://images.prismic.io/sifive/a98c5e95-3476-4cd3-9bd8-b093a30ee8c9_Slide6.jpeg?auto=compress,format)

As Cliff explained, Google has significant innovation and investment in their TPU technology, which they essentially built from “scratch” nine years ago. Recognizing the shift toward a more IP-oriented universe, Google wanted to focus on innovation in the most critical areas and where their real strengths and differentiation are, such as in the network and systolic array areas of the TPU. 

As Cliff explained, scalar and vector solutions are best left to experts in those technologies, so rather than Google reinventing the wheel, they looked for options and SiFive brought a solution. What if you could reuse a general purpose processor with a general purpose stack? Evaluating a general purpose core vs. accelerator, they looked at how, for example, you could make it easier to program. Looking at VCIX, Google saw an opportunity for flexibility and if you wanted to run Python, for example, right next to the core, you could do so with very low latency. 

He further highlighted the promise of VCIX, which is “to get accelerators and general purpose processors right close together.” Rather than hundreds of cycles for on-chip cache or thousands of cycle access through PCIe, you get the benefit of tens of cycles through vector register access.  
![SiFive and Google](https://images.prismic.io/sifive/d9248baa-8ca0-42bf-a67d-64b1432cecc8_Slide7.jpeg?auto=compress,format)
Cliff explained what he defined as an important “division of labor,” defining the technical and business operations between a companion core and MXU. A vector unit provides a wide path to memory, and much of the virtual labor is done in VCIX. There is no need to open decoders when you add the Interface overlay with its minimal instructions. And VCIX allows the sending and receiving of instructions with greater flexibility.  This flexibility and control allows a clean and efficient division of labor between the Google matrix multiplication unit (MXU) and the X280. 
As Cliff concluded, with SiFive VCIX-based general purpose cores “hybridized” with Google MXUs, you can build a machine that lets you “have your cake and eat it too,“ taking full advantage of all the performance of the MXU and the programmability of a general CPU as well as the vector performance of the X280 processor. For Google and other customers, this delivers much more programmable, and flexible future machines. 

To learn more about how X280 can **accelerate your accelerator**, contact sales@sifive.com. 


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SiFive Intelligence X280 as AI Compute Host: Google Datacenter Case Study

**The Next SiFive Revolution**

As SiFive announces its long-term plans to meet the rapidly changing needs of the automotive markets, this blog explores the many advantages the [SiFive Automotive™ portfolio](/cores/automotive) brings across a wide range of current and future applications, including; electrification, cockpit, ADAS, safety, and others. Our power efficient, flexible and high-performance cores are ideally suited for the most critical applications, and are of course, supported by the global RISC-V ecosystem.

**Why SiFive?**

Founded by the same engineers who invented the RISC-V ISA, SiFive is uniquely positioned to extend and broaden the reach of RISC-V based processors in new and growing markets. The rate of SiFive innovation and product development in the last few years has been astounding. SiFive has grown rapidly, and today offers not only the most comprehensive portfolio of RISC-V IP, but is rapidly approaching performance at the high-end that matches or exceeds any CPU IP vendor. SiFive’s growing portfolio of IP, ranging from small 32-bit real time CPUs all the way up to high-performance 64-bit application processors, singles out SiFive as the only RISC-V IP supplier that can cater to the entire spectrum of automotive compute requirements as a one stop shop. From our CEO, who grew Qualcomm’s automotive division, to our many automotive SOC experts, we are a team that uniquely understands the needs of today’s automotive manufacturer.

**A Portfolio Approach**

SiFive’s roadmap delivers a portfolio of products that meets the requirements of the vast majority of automotive CPU applications, including MCUs, MPUs and, soon, SoCs. We often read about macro trends in automotive electronic architecture design, including centralization of computing, increased compute at the sensing edge, increased SW complexity due to mixed criticality support, and a shift from domain to zonal controllers, to list but a few of today’s trends. The implications are a need for newer, more capable ECUs, and a higher degree of mixed criticality functional integration into fewer devices, at the price of increased software complexity. Despite the evolution in electronic architectures, the variety of automotive semiconductor products continues to remain broad, from small MCUs all the way to complex SoCs; however, there are significant commonalities across the many use cases including functional safety and security. Virtually every electronic device in a vehicle must comply with ISO26262, ISO21434, and additional local standards as applicable, such as UNECE WP.29 r155. SiFive Automotive products provide tailored levels of integrity, with area optimized products for both ASIL B and ASIL D, while in-field configurable integrity levels can be enabled through the available split-lock variants.

**Introducing the SiFive Automotive Family of Products**

SiFive has launched its new product portfolio and the first three SiFive Automotive product series, each with area and performance optimized variants for their intended use. SiFive is the only RISC-V IP supplier to offer multiple processor series that optimally meet automotive designers’ exact compute, integrity, and security requirements across a broad range of computing applications, from MCUs to complex SoCs.  All of the product variants offer best-in-class levels of functional safety and security capabilities, with a high degree of configurability to different integrity levels. The E6-A is the first commercially available offering. The E6-A is a 32-bit real-time core, with broad availability later in 2022. By the second half of 2023, two more product series will be added to the portfolio, the X280-A and S7-A. The X280-A is a vector capable processor ideally suited for edge sensing in ADAS, sensor fusion applications, and any ML/AI accelerated functionality in the vehicle. The S7-A is an optimized 64-bit CPU tailored for safety islands as often used in ADAS, gateways, and domain controllers. A standout feature of S7-A is native 64-bit support, meaning that the safety island can now access the same memory space as the application CPUs.

Later in 2023, a new high-end processor, configurable to up to 16-cores, will be added to the portfolio. Customers should expect best-in-class performance and ASIL support and a tailored automotive alternative for high performance CPU IP.  And much more is on the way in the coming months as the roadmap expands to meet market needs, and our SW, tools and OS partners add new levels of support.

All of the above could not have been possible without SiFive strategically adding top talent from the industry, both in CPU design and the automotive market, including, our CEO who managed the growth of Qualcomm’s automotive business, and a renowned safety expert and co-founder of Yogitech, among others. The automotive team benefits from investments in processor design that are foundational to the underlying technology, while also leveraging expertise in automotive R&D, functional safety, and security. Our team is ready to answer your automotive questions. 

**Ecosystem and Next Steps**

The automotive semiconductor market is dependent on advances from a broad range of SW, tool, and OS vendors, and their support for SiFive the RISC-V ecosystem is growing at a phenomenal pace. The ecosystem supporting RISC-V today is fast growing and reaching maturity, with many announcements in the pipeline.

SiFive is collaborating with a wide range of [automotive technology companies](/cores/automotive#partners) to create a robust and vibrant RISC-V community.

SiFive’s first automotive products are arriving in the market at a time of rapid growth and change and the company brings a modern architecture, supported by the broad global RISC-V ecosystem, with unique solutions for some of automotive’s most critical technologies. 

If you’d like to hear more, give us a call or visit our [Automotive](/cores/automotive) page for more information.




In June 2022, SiFive released an enhanced version of the market-leading SiFive® Intelligence™ X280 processor to take a further leap in performance for AI inference, image processing, and datacenter applications.

Alongside exciting new features including multi-cluster and SiFive WorldGuard trusted protection, the X280 now includes VCIX, SiFive’s new vector coprocessor accelerator interface, improving power and area efficiency, simplifying designs, and shortening design times.

The X280 shares equal success as a standalone processor as it does as a companion processor (to, for example, a custom accelerator) due to the broad range of applications that can benefit from its unique feature set that offers superior performance from the combined scalar and vector compute capabilities.

Modern workloads and applications often require the highest performance, but within a constrained power environment. Due to the excellent vector compute capabilities offered by the standard RISC-V Vector ISA and SiFive Intelligence Extensions, designers have been able to consolidate various specialized DSP accelerator functionality into a single X280 processor design thus maintaining a simpler system design and ease of programming, while still achieving the required performance and efficiency goals.

In certain situations, such as workloads requiring highly intensive computation on vector data, designers still require the use of heavily optimized custom accelerators to offload these tasks from the main processor. The challenge with this approach is that the custom accelerator needs to be designed to co-exist with the main processor, with some subtle design consequences in that the accelerator:
- will require access to, and use of an SoC system bus (for data transfers), potentially causing bus latency issues
- may need its own cache system or tightly coupled memory, for maintaining peak performance, with an associated increase in chip area
often requires a separate proprietary toolchain for programming, along with the separation of algorithm tasks increasing design time and reducing ease of programmability
![VCIX](https://images.prismic.io/sifive/40a18ebf-cbaa-4e50-9c7a-cc2f9ef7458a_Slide1.jpeg?auto=compress,format)
The SiFive Vector Coprocessor Interface Extension (VCIX) is a vector instruction-mapped interface, enabling a direct connection between the X280 vector ALU to a custom accelerator, allowing custom vector instructions to be executed on the accelerator from the vector pipeline. The custom vector instructions are executed from the standard SiFive software flow, utilizing the vector pipeline, with access to the full vector register set.



This powerful capability has many benefits to both hardware designers and software programmers as it can share some of the key processor resources, such as the vector register bank, main processor caching architecture, and memory system:
- A reduction and streamlining in both the design and test effort that is required when developing a customer accelerator due to the simpler design considerations
- Higher system performance, due to the significant reduction of computation cycles needed for specialized workloads
- Improved power and area efficiency by using the custom accelerator only when required, without the additional system area overhead 
- Easier to program, as custom vector instructions are executed from the standard SiFive software flow

Want to learn more? Contact us or access the other materials on our SiFive vectors page.
 


sifive-vectors-card-big-logo.png

Introducing the Latest SiFive® Intelligence™ X280 Processor Innovation - the Vector Coprocessor Interface Extension (VCIX)


With the 2021 launch of the SiFive® Intelligence™ X280, SiFive was the first company to release a RISC-V Vector 1.0 product, and it took the market by storm. The X280 has quickly achieved market-leading success, with design wins across a number of high performance applications including AI inference, Image Processing, and Datacenter applications. Customers include a U.S. government agency working on next generation aerospace/defense standards, a tier #1 global mobile image processor supplier, and a tier #1 global hyperscaler for AI, and the list grows daily.. 

With the latest release of the SiFive Intelligence X280, SiFive has several exciting new first-to-market features including:

- Vector Coprocessor interface: This innovative vector coprocessor accelerator interface enables better power and area efficiency with easier-to-program solutions. 

- Multi-cluster: The X280 now offers a coherent core complex of up to 4 clusters of 4-cores that scales to best-in-class multi-TOP performance.
WorldGuard: A hardware system security solution bringing trusted execution to protect AI/ML algorithms.

- Reference Platform: Introduction of the first X280 Reference Platform for reducing time-to-market for developers and the fast-growing RISC-V ecosystem

The Vector Coprocessor Interface extension (VCIX) solves two of the biggest challenges facing designers; system complexity and ease of programming:

- To reduce overall system complexity, VCIX enables designers to directly connect their own custom accelerator to the X280, utilizing and sharing the X280 processor system resources. This results in a far simpler, and more efficient, accelerator system design. 

- In order to solve the challenge of ease of programmability, VCIX enables a single toolchain to be used for programming both the X280 and the custom accelerator. As VCIX is a vector instruction-mapped interface, it gives a direct connection from the X280 vector ALU to a custom accelerator. This enables custom vector instructions to be executed on the accelerator directly from the vector pipeline as part of the standard SiFive software flow. 

Being able to share many of the fundamental processor resources, such as the vector register bank, main processor caching architecture, and memory system, brings many benefits:

- Improved the time to market due to the reduced design time for custom accelerators 

- Higher system performance for specialized workloads*
Better area optimization resulting in power and area efficiency gains

*Multi-core, Multi-cluster*

The X280 is the first RISC-V Vector processor that can be configured up to 16 cores in a coherent multi-cluster Core Complex, consisting of up to 4 cores in a coherent multi-core cluster and up to 4 coherent clusters. With these multi-core, multi-cluster configurations, SiFive also delivers the complete, configured fabric infrastructure alongside the processor to enable full coherency.

*WorldGuard*

WorldGuard, now available for the first time in a high core count system, provides a simple, yet powerful, way of enforcing hardware security by isolating code and data as well as preventing access to select peripherals. It allows different assets to be isolated into separate security worlds. This additional layer of protection can prevent rogue or bogus software running at any RISC-V privilege level, including Machine Mode, from accessing confidential data or tampering with the software. This allows sensitive firmware, like a home-grown AI/ML stack, to be isolated from more open software and also from intrusion by debug and trace capabilities.

*X280 Reference Platform*

This new resource enables easy and fast access to everything needed by SiFive customers and ecosystem partners to develop hardware and software that leverages all of the new capabilities in this latest release of the X280. The X280 Reference Platform (available in Q3) will comprise of a hardware target based on the Xilinx VCU118 FPGA board, a functional model target based on QEMU (and matching the FPGA hardware target), and a Linux-based BSP, as well as the full architectural specification of the platform. The X280 Reference Platform is intended to be easy to use by developers and the software ecosystem alike, making it easier than ever to get your application up and running with a real RISC-V vector-enabled platform. 

With the latest version of the X280, designers will continue to benefit from the success trajectory of SiFive vector processor designs, taking RISC-V and RISC-V Vectors further into new and exciting marketing applications.

For more information about SiFive vector solutions, visit sifive.com/technology/vectors. For more information about the SiFive Intelligence X280 visit sifive.com/cores/intelligence-x280


SiFive's RISC-V Leadership Strengthens with New Vector Solutions

If you haven’t seen it, SiFive is ranked in the top 10 percent of Inc.’s annual list [Here](https://www.inc.com/profile/sifive) of the fast-growing private companies in America which includes a wide range of industries. This ranking is a direct reflection of our impressive revenue growth the past three years and our momentum, forward trajectory, and leadership in the processor IP market. By the numbers, SiFive is ranked No. 413 overall, and we are excited to rank an impressive second (No. 2) in computer hardware. 

In addition to this prestigious ranking, SiFive continues to see validation from Wall Street. The company was named the first RISC-V unicorn following our Series F round of $175M and a valuation of $2.5B. We have design wins with more than 100 customers including several of the world’s largest hyperscale companies and 8 of the top 10 semiconductor companies, in applications ranging from automotive, AR/VR, client computing, data center, and intelligent edge.

“The accomplishment of building one of the fastest-growing companies in the U.S., in light of recent economic roadblocks, cannot be overstated,” says Scott Omelianuk, editor-in-chief of Inc. “Inc. is thrilled to honor the companies that have established themselves through innovation, hard work, and rising to the challenges of today.” 

According to Inc., companies on the 2022 Inc. 5000 are ranked according to percentage revenue growth from 2018 to 2021. To qualify, companies must have been founded and generating revenue by March 31, 2018. They must be U.S.-based, privately held, for-profit, and independent—not subsidiaries or divisions of other companies—as of December 31, 2021. The minimum revenue required for 2018 is $100,000; the minimum for 2021 is $2 million. 

SiFive is charting the RISC-V path for the future of compute. This win is a testament to our growth and market leadership. More to come! 


SiFive Ranks in Top 10 Percent of Inc.’s Fastest Growing Private Companies in America List 

Cambridge, with a long history of innovation and invention and a thriving tech ecosystem, is an obvious choice as a location for SiFive to continue its global expansion. We’re all about attracting the best talent, anywhere, and part of our mission and values is to also give back to, and be an active participant in the communities where we do business. As we expand in Cambridge we found a great partner with Cambridge United Football Club and this week announced our sponsorship as part of a week-long celebration. See the promotional video [Here](https://youtu.be/oh9_PX4jvC8)

![Winning combination](https://images.prismic.io/sifive/b8730eb3-e926-45e6-ae7a-f6bd5fff1f02_Large-+CU+logo+.webp?auto=compress,format)

Members of our executive and local team attended the first game of the season (they won) at Abbey Stadium which is an intimate location, steeped in history, that serves the local community.  Cambridge United Football Club competes in EFL League One, the third tier of the English professional football (soccer for you Americans) system. The club has seen meaningful success in recent years, having been promoted from EFL League Two in 2021, then exceeding all expectations in not only staying up in League One, but also upsetting Premier League Giants Newcastle United (the most expensive team in the world) in the FA cup in 2022. 

![SiFive meets the team](https://images.prismic.io/sifive/adcc6ab2-f07c-4417-bb74-a7d62e8b7ab9_52252074090_173e795eca_o.jpg?auto=compress,format)

Cambridge United's success on the pitch, with fewer resources than their competitors, mirrors the SiFive success story. The team maintains a [Community Trust](https://www.youtube.com/watch?v=vYks3_e8u1g) which is highly active in a variety of ways locally, including support of mental health education with player involvement, adaptive sports activities to drive empowerment with people with disabilities, youth volunteer training camps, senior lunches and activities, and “Over-50” community football leagues. They believe sport is a non-traditional education method and we are proud to support their efforts and look forward to a winning season. 
 
**A little education with the fun**
 
To start the week, Krste Asanovic, the founder of RISC-V and one of the founders of SiFive (and also a Cambridge Alum) gave a RISC-V overview at a crowded event at Abbey stadium where members of the Cambridge tech community dropped in to hear about technical innovations, job opportunities and other news from SiFive.
 
 ![Krste Asanovic](https://images.prismic.io/sifive/2dea7a72-16f6-4df8-8a73-926d2b3c2a5b_Krste+Speech.jpg?auto=compress,format)
 
In his talk, Krste explained how RISC-V started, how it has evolved to be a global phenomena, and how he sees it taking shape in the future. 

We recently announced our new office which will serve as a hub for R&D, engineering and marketing, and we’re actively hiring, taking advantage of the considerable tech talent in the greater Cambridge area. If you’re looking to work with an industry leader, innovator, and to change the way the semiconductor industry works, check out our open positions on our [careers page](https://www.sifive.com/careers).  



**SiFive is the market leader in RISC-V Vector processors with the flagship SiFive vector processor, the [SiFive Intelligence X280](https://www.sifive.com/cores/intelligence-x280), leading the charge as a clear favorite with customers, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.**

The X280 is gaining significant market traction due to a number of factors, including:
<ul>
<li>Design Flexibility
<li>Power and performance efficiency
<li>Portability
<li>Ease of programmability
<li>Use of standard software
</ul>

This powerful combination gives customers the ability to develop a perfectly balanced solution to tackle the demands of modern workloads and ensure market success.

The X280 processor is a 64-bit RISC-V vector processor offering best-in-class high performance and efficiency targeting AI and ML workloads. The highly configurable multi-core, multi-cluster capable design has been optimized for the broadest range of applications requiring high-throughput, single-thread performance while under the tightest power and area constraints.

![SiFive Intelligence X280](https://images.prismic.io/sifive/34f4ec15-c03a-47cc-a3b4-da5cce0b5df3_SiFiveIntelligenceX280.png?auto=compress,format)

With a specific emphasis on AI/ML compute, the X280 features the powerful combination of the RISC-V Vector (512-bit vector length) and the SiFive Intelligence Extensions, tightly integrated with an 8-stage dual-issue in-order scalar pipeline.

Key Features include:
<ul>
<li>64-bit RISC-V ISA
<li>SiFive Intelligence Extensions, which are custom instructions that accelerate AI/ML performance critical operations
<li>Multi-core, multi-cluster processor configuration options, with up to 8 cores
<li>Loosely coupled vector computation pipeline and ALU implementing RISC-V Vector extension version 1.0
<li>Support for multiple data types
<li>512-bit vector register length 
<li>256-bit Vector ALU and Load/Store architecture
<li>Decoupled scalar and vector pipelines for optimum parallel execution of scalar and vector computation
<li>Virtual memory support, with up to 48-bit addressing
<li>High performance, flexible connectivity to SoC peripherals
</ul>

See the [X280 Product datasheet](https://www.sifive.com/document-file/x280-datasheet) for full details on X280 specifics.

SiFive has a strong customer base for its vector-based product line. We have worked with customers to further define a roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, and wider vector registers. If you want to find out more about licensing the X280 then please [contact us](https://www.sifive.com/contact-sales) for more details.

Want to learn more about SiFive vectors, you can access the other materials on our [SiFive vectors page](https://www.sifive.com/technology/vectors).

If you’re excited about RISC-V Vectors and want to be part of the growing teams across the globe building the next generation of vector products from SiFive then get in touch. We have some great career opportunities in the USA, Taiwan, France, and the UK. Check out the [SiFive Careers page](https://www.sifive.com/careers) for all of the latest updates.

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

Introduction To The SiFive Intelligence X280

**After describing the current 2022 broad SiFive Performance, Intelligence, and Essential Processor Product portfolio, this webinar introduction to the SiFive vector processors begins by identifying some of the challenges that exist for system designers and subsequent evolving application trends.**

[Click here to watch the full webinar:](https://youtu.be/IxH3iqNkbQY)
[![SemiIsraelWebinar](https://images.prismic.io/sifive/2985c8a9-ca93-4f08-9027-15bfa8e57033_SemiIsraelSiFiveVectorProcessors.png?auto=compress,format)](https://youtu.be/IxH3iqNkbQY)

The semiconductor market is constantly looking to simplify design cycles while striving for more portability and re-use, broader extensibility, and increasing design scalability. In parallel, modern neural networks are rapidly and continuously evolving requiring more powerful hardware and scalable software solutions. These trends align well with the desire for more open and community-supported solutions to enable collaboration on a large scale.

The webinar also describes the benefits of RISC-V Vectors and details why they provide more optimal solutions than those based on packed-SIMD solutions and wraps up with details on the software and hardware ecosystem available supporting the SiFive vector solutions.

The introduction of the SiFive® Performance™ P270 and SiFive Intelligence™ X280 processors brings to market the first available licensable IP to support the RISC-V Vector ISA 1.0 (ratified in late 2021). 

The X280 processor is a 64-bit RISC-V Linux-capable, RISC-V Vector processor, offering best-in-class high performance and efficiency targeting AI and ML workloads. It features the powerful combination of a RISC-V Vector ISA with a 512-bit vector register length, along with the SiFive Intelligence Extensions, tightly integrated with an 8-stage dual-issue in-order scalar pipeline and decoupled vector ALU pipeline. The SiFive Intelligence Extensions operations augment and extend the standard RISC-V Vector ISA and are specifically tuned for the acceleration of neural network computation.

![SiFive Intelligence X280](https://images.prismic.io/sifive/34f4ec15-c03a-47cc-a3b4-da5cce0b5df3_SiFiveIntelligenceX280.png?auto=compress,format)

The P270 processor is a 64-bit RISC-V Linux capable, RISC-V Vector enabled, application processor, offering best-in-class performance and efficiency for the broadest range of control and vector combined computation workloads. The P270 features the powerful combination of a RISC-V Vector ISA with a 256-bit vector length, integrated with an 8-stage, dual-issue, in-order scalar pipeline and decoupled vector ALU pipeline.

![SiFive Performance P270](https://images.prismic.io/sifive/da8ba38c-f2e0-42dc-b467-fb1915b1ef08_SiFivePerformanceP270.png?auto=compress,format)

Following the 2021 release of the P270 and X280 processors, SiFive has worked closely with customers to further define and build a vector roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, along with wider vector registers. To find out more about licensing the P270 or X280, please [contact us](https://www.sifive.com/contact-sales) for more details; you can also [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors)

[Click here to watch the full webinar](https://youtu.be/IxH3iqNkbQY)

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

**A great way to get to know more about popular SiFive vector processors, which are compatible with the RISC-V Vector (RVV) version 1.0 specification**

1.) The RISC-V Vector (RVV) ISA was ratified at version 1.0 by RISC-V International in December of 2021 but it’s fair to say it’s been a big part of the SiFive and RISC-V journey and was being contemplated by the original inventors of RISC-V, namely Krste Asanovic, Andrew Waterman and Yunsup Lee, right from the beginning of the inception of RISC-V at UC Berkeley back in 2015. In fact, Krste was actually working with vectors and developing vector processors as part of his Ph.D back in the late 90s . In one of his talks about the [history of RISC-V Vectors](https://youtu.be/NlZr19lFxRg?t=12), Krste explains that there is a running joke that the V in RISC-V secretly stands for vectors. 

2.) One of the key defining features of the RISC-V Vector ISA is that it is vector length agnostic. This means that software code that has been written for any RISC-V vector compliant processor will work on any other RISC-V vector processor. From a software reuse perspective, this has a huge reward with many benefits; imagine the case where a first-generation end-product was designed around a 256-bit length vector register processor, for example, the [SiFive® Performance™ P270](https://www.sifive.com/cores/performance-p200), due to it having the perfect balance of power, performance, and area for that first design. As the product gained market success, new requirements evolved for the second generation product resulting in improved performance from the longer vector register length processor, for example, the [SiFive Intelligence™ X280](https://www.sifive.com/cores/intelligence-x280) with its 512-bit length vector registers. In this situation not only will the software code execute directly on the X280, but the code performance will improve immensely, without having to change even one line of code. This results in much-reduced design and development time, therefore a much faster time to market for the second generation product, with a very appealing faster time to revenue.

3.) The RISC-V Vector ISA is a very clean and optimized set of instructions, with the base ISA numbering around just 300 instructions, far smaller than a typical packed-SIMD alternative. Crucially these powerful instructions can each do a lot of work. The key benefits this brings are two-fold in that, 
<ul>
<li>as instruction codings take up area in a chip, this area is decreased 
<li>compilers generate very dense code, reducing the area needed for code storage 
</ul>

By minimizing this area overhead this ultimately leads to better power efficiency with a smaller memory footprint. This [tutorial video](https://www.youtube.com/watch?v=S4fxBZD79gc), while recorded prior to the final ratification of the specification, gives a great amount of detail on the overall vector ISA and explains the design philosophy and why RISC-V Vectors is considered “The best vector ISA ever!”

4.) RVV evolved to where it is today as a powerful and more efficient (in code size, performance, and area) alternative to the inefficient use of packed-SIMD and GPUs for the processing of large datasets. From its inception one of the biggest drivers was that the ISA was efficient and scalable to all reasonable design points. This meant being equally as applicable to both low-cost designs as to the highest performance applications. For this reason the ISA needed to be able to support in-order, decoupled, or out-of-order microarchitectures, along with integer, fixed-point and/or floating point data types. In a [RISC-V workshop talk in 2015](https://youtu.be/NlZr19lFxRg), Krste further explains additional design considerations for the RISC-V Vector extension as:

<ul>
<li>being a great compiler target
<li>supporting both implicit auto-vectorization and explicit programming models
<li>able to work with virtualization layers
<li>fit into standard fixed 32-bit encoding space
<li>be a base for future vector extensions
</ul>

Importantly, the design considerations were also to not replicate or be like a GPU or packed-SIMD implementation. Krste also explains some of the problems with packed-SIMD and GPU implementations, explaining how they can lead to multiple new instructions being required, therefore chip size increases, (as new data types are introduced) but also additional code required for lots of corner case handling, increasing code size (therefore bill of materials (BOM) cost), along with requiring more power.

5.) If you have existing products and software utilizing packed-SIMD code, did you know that SiFive has tools to easily port your code to RISC-V vectors? SiFive Recode can easily take code designed and written for packed-SIMD implementations and port to SiFive vectors. Additionally, for new application code, we have been very active in the open source community to offer an LLVM-based auto-vectorizing compiler, to enable faster time to market.
 
6.) As modern workloads have evolved, more complex systems have been designed with customized accelerators such as DSPs (digital signal processors) and simple finite state machines (FSM), so as to offer the best performance for specific application workloads and algorithms. Whilst the performance gain can be impressive there are a number of shortfalls to this situation:

<ul>
<li>there can be increased power and chip area due to the need for the accelerator to match the speed of the main processor by implementing a cache system
<li>the accelerator may require a separate toolchain with associated increased software complexity (and potentially software design time)
</ul>

The X280 enables consolidation of custom accelerators and control processors, resulting in a more power efficient solution and ease of use and programmability, with standard software and out-of-the-the box open source toolchains.

7.) "Standard software" - two very important words to a software developer when working on complex designs. RVV is an open standard and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and commercial grade tools for compilation, modeling, debug and trace. The upside and key benefits of this are:

<ul>
<li>access to open source algorithms
<li>standardized and stable approach to algorithm development
<li>reduced development costs
<li>and crucially, enabling much faster time to market
</ul>

8.) RVV includes a broad range of data types; including floating point, integer, and fixed point that are efficiently executed on the same single Vector ALU; this simplifies the processor architecture, resulting in improved power efficiency and reduced chip area.

9.) SiFive has a strong customer base for its vector-based product line - in fact, it is one of the fastest licensed IP product lines. Following the 2021 release of the SiFive Performance P270 and SiFive Intelligence X280 processors, we have worked with customers to define a roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, along with wider vector registers - watch out for more vector-based products throughout 2022 and beyond. If you want to find out more about licensing the P270 or X280 then please [contact us](https://www.sifive.com/contact-sales) for more details.

10.) Finally, if Vectors is your thing and you’re craving to be part of the growing teams across the globe building the next generation of products from SiFive then get in touch. We have some great career opportunities in the USA, Taiwan, France, and in the UK. Check out the [SiFive Careers page](https://www.sifive.com/careers) for all of the latest updates.

Want to learn more? [Contact us](https://www.sifive.com/contact-sales) or [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors)

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

10 Important Things To Know About SiFive Vectors

**SiFive is the market leader in RISC-V Vector processors and has gained significant market traction, with solutions being designed into a broad range of applications ranging from computer vision, mobile ISP, Edge AI, to datacenter AI.**

As SiFive vector processors become the go-to workhorse processor for modern workloads, they are being chosen for stand-alone and companion processor designs in both large and small systems. As a growing list of customers use our designs, they feed back to us their requirements for next-generation devices, and SiFive is enhancing the current portfolio as well as investing heavily in new vector processors, and a long-term roadmap to take advantage of this exciting new solution. Current customers include:
<ul>
<li>A U.S. Federal agency for next generation aerospace/defense standards
<li>Tier #1 global mobile image processor solution
<li>Tier #1 global hyperscaler for AI datacenter/learning products
<li>Tier #1 storage product developer
<li>Tier #1 global automotive infotainment solution
<li>Large U.S. semiconductor company implementing an eFPGA system
<li>U.S. eFPGA company expanding into AI DataCenter applications
<li>Tier #1 U.S. aerospace application requiring state of the art microelectronics
</ul>

Tenstorrent, an AI semiconductor and software start-up developing next-generation computers, [announced the use of the SiFive® Intelligence™ X280 processor in their future AI training and inference processor](https://www.sifive.com/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1). 

[Kinara (formerly known as DeepVision) licensed the X280](https://www.sifive.com/press/deep-vision-adopts-sifive-risc-v-to-add-opencv-enabled) (and other IP) to enhance the flexibility and functionality of their products to better support customers building applications for the fast-growing Internet of Things (IoT) markets like smart city, smart retail, automotive, and industrial.

SiFive vector processors are gaining momentum across these top-tier customers who are seeing the value and a number of key benefits. As customers share their requirements, in most cases the [SiFive Performance™ P200](https://www.sifive.com/cores/performance-p200) and [Intelligence X280](https://www.sifive.com/cores/intelligence-x280) fit perfectly well, and our roadmap instills the confidence that SiFive is looking to the future with further vector products in development now. 

Whatever your vector needs, SiFive can help! In addition to bringing trusted enterprise-ready RISC-V architecture, reduced BOM costs, and open standards, there are several key benefits that SiFive vector processors bring to designers, including:
<ul>
<li>Design flexibility
<li>Power and performance efficiency
<li>Portability
<li>Ease of programmability
<li>Use of standard software
</ul>

Let’s look at each of these in a bit more detail.

**Design Flexibility**

With RISC-V Vector Extensions, SiFive customers have tremendous freedom in both the way they design and also in the applications they pursue. The RISC-V ISA offers a compelling level of flexibility, and SiFive has capitalized on this with our product portfolio. SiFive currently has two vector products, one with 256-bit wide vectors and another with 512-bit wide vectors, along with an exciting roadmap taking us further into the higher performance market space. 

Due to the nature of the RISC-V architecture, SiFive is able to build fit-for-purpose products that align with customer requirements and application workloads. The RISC-V ISA baseline instructions number just 47, with the ability to add extensions as workloads require. This extends to the RISC-V Vector ISA, with its base ISA (numbering much less than a packed-SIMD implementation) and the ability to complement this with new workload-specific instructions, and then work with the RISC-V International team to bring this into the architecture as required. 

**Power and Performance Efficiency**

As we have seen with the flexibility of the RISC-V architecture, this also maps onto building fit-for-purpose products for our customers. Optimal system design achieves the right balance of performance for the application workload within a defined power constraint; when processing large data sets, it's about the optimum level of both scalar and vector performance. By selecting single core or multi-core, multi-cluster systems, companies are able to map this onto the required SiFive vector processor to achieve maximum performance efficiency, while meeting or exceeding their requirements for minimal area and power.

**Portability**

One of the most unique and powerful capabilities of the RISC-V Vector Extension is that the ISA is vector-length agnostic. This means that code written for a SiFive vector processor can run on any compatible RISC-V vector ISA processor, so it’s possible to experiment with different vector sizes to achieve the perfect balance of performance, power, and area for different application workloads. Also, with a growing base of open source software for vector processors, projects are easily portable between processors and applications for the same reason.

**Ease of Programmability**

A number of companies currently have designs that include one or more separate custom DSPs for performing specific application tasks. These custom DSPs needed to be designed to co-exist with the main processor, with some subtle design consequences, requiring in many cases the DSP to:

<ul>
<li>require access to, and use of the main system bus (for data transfers), potentially causing bus latency issues
<li>need its own cache system, for maintaining peak performance, with an associated increase in chip area
<li>require a separate proprietary toolchain for programming, along with the separation of algorithm tasks
</ul>

With the combined scalar and vector compute capabilities offered by SiFive vector application processors, companies have been able to consolidate the custom DSP functionality into the vector processor and still achieve performance and efficiency goals.

**Use of Standard Software**

RVV is an open standard, and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and [commercial grade tools](https://www.sifive.com/software) for compilation, modeling, debug, and trace. The upside and key benefits of this include:

<ul>
<li>access to open source algorithms
<li>standardized and stable approach to algorithm development 
<li>reduced development costs
<li>and, crucially, enabling much faster time to market
</ul>

Want to learn more? [Contact us](https://www.sifive.com/contact-sales) or [access the other materials on our SiFive vectors page](https://www.sifive.com/technology/vectors).

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

SiFive - The Market Leader In RISC-V Vectors

**The RISC-V revolution continues to advance as the technology industry embraces open computing to address semiconductor design and business challenges**

Last week saw momentous announcements, with Intel Foundry Services (IFS) enabling RISC-V alongside other processor architectures as part of Intel’s dedication to an open ecosystem and to help make IFS become one of the world’s leading foundries. By joining RISC-V International and investing significant money and resources in the open specification RISC-V instruction set architecture, Intel is empowering the RISC-V ecosystem and helping drive further adoption of open computing. A great recap of these announcements is available from [EETimes](https://www.eetimes.com/a-big-week-for-risc-v/), and you can read the Intel original news [here](https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-1-billion-fund-build-foundry-innovation-ecosystem.html), and the SiFive news [here]().
  

As always with big announcements, people want to know the bottom line - what does this mean? For SiFive, this week’s announcements mean opportunity, validation, and support for our vision of technology–a clear indication of the need for competitive processor IP to build SoCs that will support the market needs of automotive, data center, hyper scale, and edge computing platforms. Industry analysts predict there will be 25 billion RISC-V based AI SoCs in the next 5 years, representing a 34% CAGR for RISC-V CPU semiconductor IP(1).
 

We hear from our customers and partners that the need for specialized SoC design is key, along with a quick time to market. SiFive’s portfolio and approach enables a common, open standard to be the computing base, with focused products that align the hardware to the software. There is no incumbent in these market opportunities, enabling RISC-V and SiFive to win on our merits - something we are truly excited about! 
 

**Developing for RISC-V**

SiFive had a breakout year in 2021, as we entered performance-driven markets with new products to be part of the high-value silicon blocks that deliver the experiential uplift. We launched the SiFive Intelligence™ family in Q2 of 2021 and now have several licensees, following our first public win with AI leader Tenstorrent. Similarly, the SiFive Performance™ P550 has multiple licensees including Intel, as part of the IFS “Horse Creek” platform and SoC. Delivering 3x more performance per area than our competitor’s core, as well as being the fastest commercially available RISC-V processor IP at launch, contributed to why the SiFive Performance P550 will be at the forefront of Intel’s RISC-V development platform. We saw firsthand the power of seeding the industry with our SiFive HiFive line of developer boards, and our partnership with Intel will take those efforts to the next level.
 

As an IFS Accelerator - IP Alliance partner, SiFive will offer our industry-leading portfolio of RISC-V-based processor IP to customers of IFS, supported by our partnership with Intel’s $1B innovation fund, a collaboration between Intel Capital and IFS. In addition to investing in disruptive startups, Intel will dedicate expert open source software developers to collaborate with SiFive to enhance and grow the RISC-V ecosystem, using the “Horse Creek” Development system powered by SiFive Performance P550 processor cores.


**The Open Computing Era**

The RISC-V instruction set architecture was invented over a decade ago to enable freedom to innovate and avoid the pitfalls of proprietary technology, and SiFive is the vehicle the inventors of RISC-V has chosen to explore the commercial opportunities of the open specification. The open approach of RISC-V is combined with the collaborative nature of RISC-V International and the technical groups to enable contributions from many parts of the world. As part of these groups, premier members like SiFive and Intel are able to openly help develop the specifications and extensions that all parts of the RISC-V ecosystem can implement. From hardware to software, the open specification of RISC-V ensures an era of open computing is enabled.
 

This is what I mean by the headline “investment heard around the world.” We’re well past the time of “Is RISC-V going to take off?” and into “How high can it go?” The answer is that RISC-V has no limits, and SiFive is eager to show what our immensely talented team is capable of. We’re hiring at many levels and we’d love to hear from you if you think you’d be a good fit - please see our career options, [here](https://www.sifive.com/careers). This year, we’re going to deliver on our promise to bring the SiFive Performance P650 (2) to market, and continue to innovate and extend our performance leadership in RISC-V!
 

Footnotes:

1 - SemiCo Research report CC330-21, “[Analyzing the RISC-V CPU Market for SIP, SoCs, AI and Design Starts](https://semico.com/content/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts)”

2 - Case study from The Linley Group by Techinsights, "[SiFive P650 Pumps Up Performance by 50%](https://www.sifive.com/resources/case-studies/sifive-p650-pumps-up-performance-by-50)" 
  

SiFive_Blog_Feb142022.png

**SiFive joins the Intel Foundry Services IP Alliance program to broadly enable innovative new computing platforms**

In 2021, SiFive evolved our industry-leading RISC-V portfolio of processor IP into three families, each with a focused purpose. The [SiFive Essential™](https://www.sifive.com/cores/essential), [SiFive Performance™](https://www.sifive.com/cores/performance), and [SiFive Intelligence™](https://www.sifive.com/cores/intelligence) families leverage the expertise of our company founders who created RISC-V and our talented engineers to build products that will address the entire semiconductor industry, from embedded applications to performance-driven uses and applications powered by AI/ML. The SiFive portfolio of RISC-V processors enables choice in the pureplay IP market to enable computing platforms optimized for the market application. 

As part of the mission to expand RISC-V to every market and application, SiFive works with leading semiconductor foundries to enable their customers to quickly adopt SiFive technology and optimize their designs. We’re excited to announce that SiFive is partnering with Intel Foundry Services (IFS) [Accelerator – IP Alliance program](https://www.intel.com/content/www/us/en/foundry/ifs-accelerator.html), to optimize SiFive IP for IFS customers and deliver maximum performance and value from both technologies. 
 
SiFive previously announced [a collaboration with Intel](https://www.sifive.com/blog/sifive-collaborates-with-new-intel-foundry-business) using the [SiFive Performance P550](https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest) processor to build a RISC-V development platform, codenamed “Horse Creek,” combining Intel’s leading-edge interface IP such as a PCIe® and DDR with SiFive high-performance CPU IP. We’re excited to extend our relationship with IFS to ensure the full SiFive RISC-V processor portfolio is available to IFS customers, including the recently announced [SiFive Performance P650](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class) processor. As the world’s fastest commercially available RISC-V processor IP, the SiFive Performance P650 extends RISC-V into new markets including automotive, AI/ML, client computing, data center, and mobile, among others. To stay informed on updates on the “Horse Creek” RISC-V developer board, please register [here](https://www.sifive.com/horse-creek-updates). 
 
“We are pleased to announce the IFS Ecosystem Alliance as a major step forward for Intel's foundry ambitions,” said Rahul Goyal, VP and GM of Intel Product & Design Ecosystem Enablement. “We are excited to have SiFive join the alliance. We look forward to partnering with SiFive to extend their leadership IP with IFS for the benefit of our mutual customers world-wide.” 

You can learn more about the SiFive portfolio in our recent presentations at the RISC-V summit, available for replay on YouTube here:
<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
</ul>

At SiFive, you can work alongside experienced industry leaders and the inventors of RISC-V. We encourage you to consider SiFive as the next stage of your career, as we look for talented individuals in many areas to help accelerate our mission of greater choice in the pureplay processor IP market. You can view our career options [here](https://www.sifive.com/careers). 

Stay current with the latest SiFive updates via [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

IFS-SiFive-Blog-1080x1080-Feb2022.png

**SiFive is aiming high with bold new technology for performance-driven applications**

SiFive transformed in 2021 and grew from leading RISC-V for embedded products into performance-demanding markets, creating real choice in the semiconductor processor IP market. Now, the SiFive portfolio features three distinct, market-focused product families, based on market requirements ranging from high-performance applications, machine learning and artificial intelligence processing, to embedded real-time deterministic and small application processors. Our RISC-V IP portfolio is designed around our focus to deliver processor IP for these demanding markets, combining the unlimited potential of RISC-V with the experience and talent of our team. 

This rapid progress was made possible by our partners and customers who believe and invest in RISC-V and the freedom it represents for technology. RISC-V has no limits, and all of us at SiFive are thankful and grateful for all our partner’s support in creating new products for the untapped potential of new and fast growing markets. In 2021, we reached significant milestones for our company with over 300 design wins at more than 100 companies, including 8 of the top 10 semiconductor companies; and we launched our new SiFive Intelligence™, SiFive Performance™, and SiFive Essential™ product brands with class-leading products in each family. 

**A Breakout Year** 
In 2021 we launched several new products. Most recently, we expanded the SiFive Essential family with the introduction of the SiFive Essential 6-Series processors, designed for mid-range applications; we also introduced the SiFive Performance P650, our fastest RISC-V processor, which will be available to lead customers in Q1 2022. Earlier this year we launched the SiFive Intelligence X280 for AI/ML markets, featuring SiFive Intelligence Extensions that build upon the RISC-V Vector extension to provide a platform for AI & ML with enhanced data types and support for TensorFlow Lite. The SiFive Intelligence X280 is a great inference processor and may be combined with existing hardened AI IP to enhance programmability and scalability by offering scalar and vector capabilities. The SiFive Performance P550 and SiFive Performance P270 processors for performance driven markets were also introduced in 2021, with up to 8-core coherent clusters and multiple clusters in an SoC, with heterogeneous mix+match options to allow for the right mix of processing capabilities. 


The RISC-V ecosystem has moved forward significantly in 2021 with important specifications ratified that unlock and enable hardware and software development in key markets. Working alongside the RISC-V community has been a pleasure for the many SiFive employees who contribute to the technical groups that develop RISC-V specifications as we all work together to build the technology and tools needed for virtualization, advanced interrupts, vector processing, and more. 

Building IP based on these new specifications is a key goal for SiFive, enabling our customers to quickly adopt the ratified standards. In 2021, SiFive offered three releases using our relentless innovation methodology to deliver new features in a software-like manner across our portfolio. SiFive increased efficiency and performance across our RISC-V processors, and introduced new features for cluster scalability, security, advanced power monitoring and control, and virtualization. 

**Raising The Bar in 2022** 
In 2022, we’ll continue to deliver high performance processor IP that will enable the creation of new computing platforms. From the metaverse to autonomous vehicles, natural language processing, recommendation systems, client computing devices and more, there is massive demand for RISC-V. We’re making the most of this demand by continuing to deliver high-performance processor IP packed full of performance and accompanied by the features our customers and partners require. If you didn’t catch them already, you can see some great pointers on what we’re doing in these talks from the 2021 RISC-V Summit: 

<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=-0xQ63xD3zA>Keynote: RISC-V State of the Union</a> (Krste Asanovic, Co-Founder & Chief Architect, SiFive, and Chairman of the Board, RISC-V International)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=be5zBe-UHds>Continuous Innovation in Embedded RISC-V Processors</a> (Drew Barbier, director, product marketing, SiFive)</li>
</ul>

If you’d like to be part of the rapid rise of RISC-V, SiFive is looking for talented individuals in many areas. You’ll work alongside the inventors of RISC-V and leaders in the semiconductor industry as we design, develop, and deploy RISC-V technology for a variety of computing challenges. Please look at our careers page here for more information and take the next step to be part of the unlimited future of RISC-V! 
 
We wish all of you a prosperous and happy 2022! Keep up with SiFive news and announcements on social media: [Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc).

SiFive_Blog_RapidRiseOfRISCV_Jan2022.png

**The RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits!**

2021 has been an outstanding year for SiFive, and the biggest in its history, starting with the introduction of the AI/ML focused [SiFive Intelligence™](https://www.sifive.com/cores/intelligence) and high performance [SiFive Performance™](https://www.sifive.com/cores/performance) series of processors and culminating with the announcement of the [SiFive Performance P600](https://www.sifive.com/cores/performance-p600) and latest SiFive 21G3 release as part of the RISC-V Summit 2021.
 

**Specifications** 
In parallel, RISC-V International has ratified an impressive [fifteen new specifications](https://riscv.org/announcements/2021/12/riscv-ratifies-15-new-specifications/). The new RISC-V Vector extension, as seen in the SiFive Intelligence X280 and SiFive Performance P270 products, and the RISC-V Hypervisor specification, now available in the SiFive Performance family of processors, are key technology enablers that will drive the continued growth of SiFive adoption further into an ever broadening range of applications and market segments. 

**Performance**
After a sneak peek at [The Linley Group Fall Processor Conference](https://www.tomshardware.com/uk/news/sifive-develops-ultra-high-performance-risc-v-core) back in October, SiFive recently took the wraps off our latest high performance processor, the [SiFive Performance P600](https://www.sifive.com/cores/performance-p600), SiFive's flagship product for 2022. The SiFive Performance P650 highlights SiFive’s commitment to continuously innovate and deliver a high-performance roadmap of RISC-V processors, and achieves a [leap in performance overall of over 50%](https://www.sifive.com/press/sifive-raises-risc-v-performance-bar-with-new-best-in-class) in just one year when compared to the SiFive Performance P550. 
The SiFive Performance P650 further extends its reach into the ultra high end market with a best in class 11+ SPECint2k6/GHz benchmark score, making the SiFive Performance P650 the highest performance licensable RISC-V processor. 
The SiFive Performance P650 will offer scalable performance with multi-core, multi-cluster processor configurations initially up to 16 cores, and includes the recently ratified Hypervisor extension. Our roadmap will, over time, extend to many-cluster capabilities that deliver 128-cores, or more, in an SoC.

**Relentless Innovation**
The SiFive 21G3 release includes the launch of the mid-range [SiFive Essential™](https://www.sifive.com/cores/essential) 6-series processor family along with a stack of further enhancements, including multi-cluster capability for the SiFive Performance family and SiFive Intelligence family.

The SiFive Essential 6-series is an eight-stage, single issue, in-order pipeline processor family targeting mid-range performance markets. The SiFive Essential 6-Series continues to deliver on SiFives’s commitment and investment in best in class performance processors with advanced features and configurability options including; RISC-V ISA B Extension for improved performance and code-density, and an optional half-precision FPU unit for area constrained applications, along with separate instruction tightly integrated memory (ITIM) and Instruction Cache (with an option for removing the i$ for specific market requirements).

![SiFive Essential Family](https://images.prismic.io/sifive/4d90a7c0-839b-44f5-96b5-59fe2f2380d9_SiFiveEssential762family.png?auto=compress,format)

The SiFive Performance P550 has gained a 10% increase in maximum frequency improvement and 10% dynamic power reduction as part of the latest release, achieving a 8.7+ SpecINT2k6/GHz benchmark, the market leading highest single thread performance metric. 

In AI/ML markets, the SiFive Intelligence X280, launched earlier this year, is already being designed into a multitude of machine learning products. To further extend its market applicability, BFLOAT16 matrix multiplication compute and quantization acceleration have been added to the SiFive Intelligence Extensions, delivering significant performance improvements across a wide range of machine learning workloads.

**Reach The Summit**
For SiFive, RISC-V, and the whole IP industry, 2021 was an inflection point with the expansion from great achievements in embedded control type applications to the opening up of the markets with ultra high-end processors like the SiFive Performance P550 & SiFive Performance P650, and AI/ML compute with advanced vector computation covered by the SiFive Performance P270 and SiFive Intelligence X280. The SiFive Performance P650 has raised the bar for high-performance and sets the stage for a phenomenal 2022 - stay tuned for more innovation announcements next year.

**SiFive Presentations at the 2021 RISC-V Summit**
SiFive delivered presentations and keynotes at the 2021 RISC-V Summit event highlighting the impressive progress and unlimited promise of RISC-V. You can view a representative few without a login required: 
<ul> 
<li> <a href=https://youtu.be/jZ-1i9ZoSZ4>Keynote: The Future of RISC-V Has No Limits</a> (Yunsup Lee, Co-Founder & CTO, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=-0xQ63xD3zA>Keynote: RISC-V State of the Union</a> (Krste Asanovic, Co-Founder & Chief Architect, SiFive, and Chairman of the Board, RISC-V International)</li>
<li> <a href=https://www.youtube.com/watch?v=UsiWahIy-r4>Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications</a> (Shubu Mukherjee, VP Architecture, SiFive)</li>
<li> <a href=https://www.youtube.com/watch?v=be5zBe-UHds>Continuous Innovation in Embedded RISC-V Processors</a> (Drew Barbier, director, product marketing, SiFive)</li>
</ul>

**Keep Climbing**
I joined SiFive this year after spending more than twenty years’ in the IP industry, and I am wildly excited about the technology, growth opportunities, and direction SiFive is taking. As the first UK employee, I’m thrilled to see more people eager to join and the team expanding; if you’re interested in joining me and embracing the challenge here in the UK, USA, or further afield, check out the career opportunities at [SiFive.com/Careers](https://www.sifive.com/careers).

sifive-blog-logo.png

## The freedom of RISC-V enables a bright future for SiFive

What a time to be in the Semiconductors and CPU industry! As an industry, we are experiencing a perfect storm. With the rise of machine learning, cloud computing, and autonomous driving; the need for advancement in computing has never been greater. This is happening at a time when Moore’s law has considerably slowed and dennard scaling has come to an end. Architectural innovation is required to break out of the current logjam, but the closed nature of proprietary ISAs that have dominated our industry for three decades are unwieldy and unsuitable for application-specific computing needs going forward. 

> *"Moving forward, the logical path is to add extensions to the basic instruction sets on microprocessors for application domains"* 
> - [David Patterson](https://cacm.acm.org/magazines/2020/5/244325-will-risc-v-revolutionize-computing/fulltext?fbclid=IwAR2gT41IiQM9WUnP4gmgcUrgEhra2rE4I9MjwJjbmOchw26Ij0v6-WMauPQ) (Computing pioneer, Turing award winner, and father of RISC architecture), speaking to **CACM**

The open nature of the RISC-V ISA coupled with SiFive’s best-in-class design methodology makes it an ideal place to build the next computer. SiFive is already the premier supplier of RISC-V CPU to the industry, with 300+ design wins, 100+ customers, and 8 out of the top 10 semiconductor companies and I’m super excited to have the opportunity to be a part of this revolution. 

Today I’m thrilled and proud to announce that I have joined SiFive to lead the Engineering team to build the best-in-class processor IPs that will be at the heart of future computing platforms.

I’ve been lucky to be associated with both of the major computing platforms of the last 25 years. First at AMD, where I worked on their highest-performance x86 CPUs, and then at Apple, where I led the implementation of CPU IP in the A5X through A13 SoCs. It was humbling to have the opportunity to lead the first implementation of the 64-bit mobile CPU (cyclone) that changed the world. During this journey, I pioneered many low power design techniques and we hired & built one of the best CPU design teams. Fitting desktop CPU performance into a phone power envelope required re-thinking everything from architecture to floorplan to clocking to std cell library choices and novel ways to visualize power so the entire team could focus on power-first design. 

At SiFive we’re building best-in-class CPUs with a full range of performance options that give our customers more choice & flexibility. I’m looking forward to [scaling the team](https://www.sifive.com/careers) to achieve new heights in performance and power efficiency. To learn more about our capabilities and products, please come see me at the [RISC-V Summit](https://events.linuxfoundation.org/riscv-summit/register/), Dec 6-8.

RohitKumarIntroBlog111921.png

## In just a few short years, RISC-V has become a category of utmost importance in tech; but, things are just getting started.

In 2014, the inventors of RISC-V (and founders of SiFive) published a very [“modest”](http://people.eecs.berkeley.edu/~krste/papers/EECS-2014-146.pdf) goal: for RISC-V to become the standard ISA for all computing devices. Ambitious at the time, but now we can confidently state that RISC-V has made its impact in our industry and is here to stay. RISC-V has become hugely important – strategic to companies and governments alike – and has already made its way into billions of chips and thousands of companies.

And… we’re just getting started.

This week, you may have noticed SiFive unveiled a new look on our website and a clear focus on high performance as we continue to drive RISC-V forward and define the future of compute. RISC-V is inevitable, and we are accelerating that timeline.

To our internal teams, this energy, aggressiveness, and decisive roadmap is nothing new. We’ve been building successful products for years, and now we’re growing faster than ever. Our resolve has never been stronger: to build the best-in-class processor IP that will be at the heart of future computing platforms — from artificial intelligence, machine learning, automotive, data center, mobile, to consumer markets. As we rapidly accelerate our performance capabilities, RISC-V truly will have no limits.

I’ve never been prouder of SiFive’s talented, passionate, and forward-thinking engineering and product teams. We’ve built a world-class portfolio of processor IP with over 300 design wins at more than 100 different customers around the world, including 8 of the top 10 semiconductor companies.

To our customers: thank you for being part of our journey and shared vision of the future. We’re honored by your trust and partnership, and we hope we’ve delivered an incredible customer experience along the way; but, buckle up, because we’re about to turn the corner and take RISC-V to new heights of performance and capabilities. 

We’ll share more about our future plans at the upcoming [RISC-V Summit](https://events.linuxfoundation.org/riscv-summit/) on Dec 6-8, including details on our next-generation processor architecture that will be our fastest processor ever. We’re also hiring—across all positions and all career levels to accelerate our journey. If you’d like to work alongside the creators of RISC-V, collaborate with top industry partners, and help create the future of RISC-V, we invite you to [join us.](https://www.sifive.com/careers) 

The future of RISC-V has no limits. And I, for one, couldn’t be more excited!

JackKangRISC-VisInevitable.png

## Scalable High-Performance Computing SoC Design with RISC-V

Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.

[The technology industry is shifting](https://www.cnbc.com/2021/09/06/why-tesla-apple-google-and-facebook-are-designing-their-own-chips.html) to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA). Enabling this industry shift is central to SiFive’s mission and why SiFive’s founders invented RISC-V a decade ago.
 
**Bet on yourself with RISC-V Chiplets**
Based on an easily extensible open specification, the RISC-V ISA lets semiconductor companies “bet on themselves” by leveraging targeted microarchitecture development to enable a developer-friendly approach to hardware and SoC design. Because software and hardware meet at the instruction set architecture, the open specification RISC-V ISA permits freedom of adoption, vendor, extension, and customization; key traits shared with successful open technologies, such as Ethernet or Linux.
 
SiFive is the leading provider of RISC-V-based processors and accelerator IP and is home to the inventors of RISC-V and LLVM. As part of the RISC-V Vector extension task group, we’re excited to drive and see worldwide adoption of RISC-V Vectors as a path to creating AI and ML-focused products in markets such as AIoT, automotive, aerospace, networking, storage, hyperscale computing, and the data center. SiFive is betting on ourselves to deliver high-performance, high-quality RISC-V-based IP that will enable next-generation computing platforms.

With over 200 design wins and a billion cores shipped, technology companies can double down on that bet by working with SiFive and granting themselves the freedom to innovate.
 
**AI in the data center and HPC**
Workloads well-suited for processing on chiplets need die-to-die (D2D) communication to support the bandwidth requirements of the datasets. Combined with the advanced 2.5D packaging solutions from OpenFive, a SiFive business unit, and high performance, low power, and low latency HBM/D2D interface IP, designers can now create systems-on-chip (SoCs) that pack more compute power into smaller form factors for AI and HPC applications.
OpenFive delivers highly competitive SoCs with its spec-to-silicon design capabilities, customizable IP for AI/Cloud/HPC/storage/networking applications, and processor-agnostic, domain-specific architectures. 
The OpenFive IP portfolio includes: 
- Die-to-Die (D2D) interface IP for multi-die connectivity, including chiplets 
- High-Bandwidth Memory subsystem (HBM2/E & HBM3)
- Low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity 
- 800/400G Ethernet MAC/PCS subsystems 
- USB controller IP

**Architecting the Future**
The SiFive portfolio leads the industry as the broadest and most advanced RISC-V-based portfolio of processor IP, from the minds that created RISC-V. With [leading companies](https://www.tomshardware.com/uk/news/apple-looking-for-risc-v-programmers) implementing RISC-V-based designs for machine learning, computational vision, natural language processing, and other tasks, the need for scalable, flexible microarchitectures extends across many markets.

![RISC-V Chiplet Architecture Diagram](https://images.prismic.io/sifive/f3b221b4-135b-4595-ad2a-c22dd13d51b6_RISCvchipletsoutlineblog.png?auto=compress,format)

**SiFive RISC-V Chiplet Architecture IP**
- SiFive Performance™ family
 * [SiFive Performance P550](https://www.sifive.com/cores/performance-p550)
 * Advanced Out-of-Order 13-stage, triple issue pipeline
 * SPECInt 2006 8.65/GHz
 * Highest performance commercially available RISC-V processor _(1)_
 * [SiFive Performance P270](https://www.sifive.com/cores/performance-p270)
 * 8-stage, dual-issue, superscalar pipeline
 * 256b Vector unit for versatile compute capabilities
- SiFive Intelligence™ 
 * [SiFive Intellligence X280](https://www.sifive.com/cores/intelligence-x280)
 * 8-stage dual-issue, superscalar pipeline
 * 512-bit Vector unit with SiFive Intelligence Extensions to supercharge ML performance _(2)_
 * Support for BF16/FP16/FP32/FP64, int8 to 64 fixed-point data types
- SiFive Recode™
 * Creates SiFive RISC-V Vector code from legacy Arm® Neon™ code to protect your existing software investment and migrate with confidence
- SiFive Essential™ family
 * [SiFive U/S/E class processors](https://www.sifive.com/cores/essential)
 * U class cores for 64-bit Linux-based application platforms
 * S class cores for 64-bit embedded applications
 * E class cores for 32-bit embedded applications
- OpenFive Die-to-Die Subsystem
 * Low latency, low-power, interface supporting up to 4Tbps/mm
 * Multi-cluster CPU connectivity
 * Network-on-Chip interface with support for AMBA® AXI and other coherent interfaces
 * Scalable, reliable links with very low BER, supporting end-to-end error correction & retransmission
- OpenFive High-Bandwidth Memory Subsystem
 * 7.2Gbps speeds for HBM3 standard

[SiFive](https://www.sifive.com/) enables RISC-V-powered chiplet designs for AI/ML products today, accelerating the design of new high-performance computing platforms and is leading the [RISC-V uprising](https://www.forbes.com/sites/karlfreund/2021/09/08/if-the-arm-deal-fails-nvidia-is-fine-but-arm-may-struggle/).

*1 – SiFive Performance P550 processor measured at 8.6 SpecINT2k6/GHz by SiFive engineering, July 2021.
2 – Matrix Multiplication Kernel (int8) execution time in common benchmark measured by SiFive engineering using SiFive Intelligence X280 processor vs. RVG64GCV RISC-V Vector configuration.
All trademarks referenced herein belong to their respective companies. Arm®, and Neon™ are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.*

RISCVchipletsdisaggregateddietiles.png

RISC-V Chiplets, Disaggregated Die, and Tiles 

# Leading the RISC-V uprising drives SiFive, home of the inventors of RISC-V, to continue to push forward with developing our product families and technologies.

## RISC-V for High-Performance Applications 
Earlier this year, we debuted the [SiFive Intelligence](https://www.sifive.com/cores/intelligence) family at the Linley Group [Spring Processor Conference](https://www.youtube.com/watch?v=3WyMdegWgh8), including one of our [lead customers, Tenstorrent](https://www.sifive.com/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1), who will integrate the [SiFive Intelligence X280](https://www.sifive.com/cores/intelligence-x280) in a future product line. In June, we introduced the [SiFive Performance](https://www.sifive.com/cores/performance) family of processors, including the [SiFive Performance P500](https://www.sifive.com/cores/performance-p500) and [SiFive Performance P200](https://www.sifive.com/cores/performance-p200). 

With the SiFive 21G2 release, we are pleased to invite designers to evaluate these new processors, as well as discover the 21G2 release enhancements to the [SiFive Essential processor family](https://www.sifive.com/cores/essential). From the fastest RISC-V commercial processor IP available today, the SiFive Performance P550(1), to the newly enhanced SiFive Essential product lineup, SiFive offers the broadest and most capable RISC-V-based processor portfolio. We continue to work with technology innovators and industry leaders to develop new products that will push the envelope of computing capabilities. 

To ease smooth adoption of this new technology, SiFive Recode automatically translates existing Arm® Neon™ code to RISC-V Vector code for the SiFive Intelligence and SiFive Performance products that offer RISC-V Vector extension execution capability. Included in the SiFive Freedom toolchain are GCC and LLVM compilers specifically designed to help write software optimized for RISC-V and the RISC-V Vector extension. 

[Join us in September](https://community.riscv.org/events/details/risc-v-foundation-risc-v-forums-presents-risc-v-forum-vector-and-machine-learning) at the RISC-V Forum for RISC-V Vectors and Machine Learning to learn more about the potential for RISC-V Vectors, an open specification developed by Industry-leading companies & researchers, to address modern computing challenges. 
 
## Making Development Easier 
Developing ahead of silicon availability is key to a smooth and fast product development cycle. SiFive includes and supports Linux FPGA bitstreams with its SiFive Performance, Intelligence, and Essential application processors. The Linux software development platform is based on the Xilinx VCU118 to provide a fast, no-hassle mechanism to evaluate SiFive cores in an off-the-shelf environment. Included with the processor core bitstream is a functional peripheral subsystem, including common interfaces, and [SiFive Insight](https://www.sifive.com/technology/sifive-insight) Advanced Trace and Debug to enable processor evaluation. The SiFive Freedom SDK enables application development and workload modeling to help product evaluation as you program the FPGA, build your SD card, and boot into Linux to get started. 

## SiFive Relentless Innovation 
Driven by the market demand for workload-focused designs, SiFive processor cores are configurable with unmatched options for workload tuning. Our innovative methodology and automation enable us to deliver not just new products like the recently announced SiFive Performance family of processors, but also enhance and advance our existing product families. You can license access to cores, families, or the entire portfolio, ensuring you have the flexibility and scalability you need to fuel your product roadmap. 

We call this process SiFive [relentless innovation](https://www.sifive.com/risc-v-core-ip), and it’s the backbone of the SiFive 21G2 update that offers many new features and enhancements that are [now available](https://www.sifive.com/resources/webinar/introducing-sifive-performance-family). 

## Faster is Essential 
The SiFive Essential 7-series processor cores continue to offer enhanced performance, without significantly impacting power or area. With the SiFive 21G2 release, SiFive Essential 7-series processors offer up to 11% more performance than the 21G1 release(2), thanks to the enhanced design updates that reduce latency and improve instruction throughput. These performance improvements deliver important increases in efficiency for SiFive Essential 7-Series processors, which have applications in many markets including computational storage, edge computing, IoT, network baseband, virtual reality, and more.

## Programmable Remapping 
SiFive Essential S7, E7, S5, E5, S2, and E2 embedded and control processors now offer software programmable address remapping to enable data region remapping and ROM code patching, with support for both instruction and data addresses. The address remapper is configurable to provide a balanced trade-off between area use and functionality, offering up to 64 remap regions that can scale from 4 bytes to the full address space. 

The SiFive Essential family is silicon-proven IP in the world’s leading foundries, and offers SiFive Insight advanced trace and debugging capabilities to make it easy to integrate and productize RISC-V-based processors. For more information on the SiFive products discussed today, please watch our webinar replay, available now. 

Footnote 
1 - Based on SiFive Internal Engineering measurement of a geomean score of 8.65 SPECint2k6/GHz and 9.4 SPECfp2k6/GHz by SiFive Performance P550 in emulation using maximum performance configuration with simulated memory subsystem at 100ns memory latency (load to use) running the full SPECit 2006 benchmark. 
2 - The SiFive Essential 7-series 21G2 processors offer up to 11% higher score, comparing aggregate percentage increase of CoreMark/MHz and Dhrystone/MHz scores versus the 7-series 21G1 release processor scores, as measured by SiFive internal engineering team: SiFive U7 & S7 21G2 = 5.7 CoreMark/MHz & 3.2 Dhrystone/MHz; SiFive E7 21G2 = 5.7 CoreMark/MHz & 3.0 Dhrystone/MHz; SiFive U7 & S7 21G1 = 5.2 CoreMark/MHz & 2.8 Dhrystone/MHz; SiFive E7 21G1 = 5.2 CoreMark/MHz & 2.6 Dhrystone/MHz. 
All trademarks referenced herein belong to their respective companies. Arm and Neon are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

SiFivePIE-Square.png

Delivering on the Promise of Industry-Leading RISC-V Processors

## Introducing the new era of SiFive Performance for RISC-V

When I joined SiFive last year, I found a dedicated team working on great technology with a vision to do no less than to change the world.

As I talked to our customers and partners, it was clear that while we had satisfied users, the industry expected and desired greater things from SiFive. The message was loud and clear that SiFive needed to push the boundaries of what’s possible to bring high value, differentiated products to market. I knew that my job was to then enable and support our incredible collection of talent with the tools and resources needed for us to execute at a high level. 

This week marks an important milestone toward that mission, with the unveiling of new products that showcase our capabilities, reinforce our strategy, and are available today for evaluation and licensing. The announcement of the SiFive Performance family of processors heralds the arrival of a new era for both SiFive and for the RISC-V movement. Long gone are the days where RISC-V is only suited for cost-down replacements of legacy 32-bit architectures; from this point forward, SiFive and the RISC-V ISA will be mentioned in the same breath as the processor architectures that are powering today’s phones, laptops, and data centers. 

The arrival of the [SiFive Performance](https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest) family of processors is proof that we’ve entered a new phase at SiFive, as we have just now delivered to lead customers the highest performance licensable RISC-V processor in the industry. However, “Performance” is more than simply a brand name for application processors with enviable benchmark scores; it represents an initiative within our company to continue to innovate to bring the highest possible performance processors to our partners’ SoCs. 

![SiFive PIE](https://images.prismic.io/sifive/ac74ec7b-d0b8-457b-9fa9-8f6849052cc9_SiFivePIE-Overview.png?auto=compress,format)

Followers of SiFive may recall that in April we announced another key initiative we call “Intelligence”; a software-centric approach to unleashing the power of RISC-V vector computing for machine learning applications. With our [SiFive Intelligence](https://www.sifive.com/cores/intelligence) X280 processor and support for popular CNN frameworks, we’re already enabling customers building machine learning silicon for both training and inference, in the datacenter and at the edge. 

I’d be remiss if I didn’t mention our portfolio of processors that have laid the groundwork for the innovation that we’re bringing to market today. These products that have been a part of 200 design wins are still a critical part of our journey and continue to evolve and improve with each new release. Going forward, we’ll refer to these fantastic and broadly adopted products as the [SiFive Essential](https://www.sifive.com/cores/essential) family of processor cores. 

Performance, Intelligence, Essential — words that demonstrate our vision, our mission, and our strategy. Now is an exciting time to work at SiFive. I encourage you to contact us to learn more about our great products, to watch our [upcoming webinars](https://www.sifive.com/resources/webinar/introducing-sifive-performance-family), and to let us know via social media how we’re doing . As we continue our business and technology growth, we’re hiring – please join us on our exciting journey! 

Stay tuned for more exciting announcements in the coming months: 
[Facebook](https://www.facebook.com/SiFive/), [Instagram](https://www.instagram.com/sifive_inc/), [LinkedIn](https://www.linkedin.com/company/sifive), [Twitter](https://twitter.com/SiFive), and [YouTube](https://www.youtube.com/c/SiFiveInc)

The Heart of SiFive is Performance, Intelligence, & Essential

**Introducing the SiFive Intelligence X280**

This week has been an exciting one for our team at SiFive, with a number of key announcements that are beginning to allow us to publicly share our strategy for the exponentially growing AI/ML market. While we are only scratching the surface of the impact AI/ML will have on our industry and our lives, it’s clear that the workloads, algorithms, and requirements are going to be constantly evolving and improving for the foreseeable future. 

These changing requirements make it exceedingly difficult to align workloads with purpose-built silicon. Hardwired accelerators may work well for matrix multiplication and convolution layers today but simply aren’t efficient or adaptable enough for more modern models, such as transformer-based models like BERT or recommendation models. What’s needed are adaptable AI and ML solutions with a flexible, future-proof approach enabled by efficient, programmable building blocks of hardware IP designed with a software-first ideology. 

This leads us to our biggest announcement this week, SiFive Intelligence. Today at the Linley Spring Processor Conference, Dr. Chris Lattner, President of Engineering and Product at SiFive, introduced the SiFive Intelligence X280. The SiFive Intelligence X280 extends RISC-V with SiFive Intelligence Extensions, integrating dedicated AI acceleration technology and extended data type support. SiFive Intelligence includes turnkey software solutions that utilize the X280's features to provide great AI inference performance and support for the full capability of TensorFlow Lite. The result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of popular machine learning models. 

We’re pleased to debut SiFive Intelligence and to be able to tell you that one of the first customers of the SiFive Intelligence X280 is AI developer Tenstorrent, an innovator in AI training and inference processors led by industry leaders Ljubisa Bajic and Jim Keller. The heterogeneous combination of Tenstorrent’s Tensix processing cores alongside the SiFive Intelligence X280 will bring efficiency and programmability to stay ahead of the requirements of next-generation AI workloads. Read more about [SiFive's collaboration with Tenstorrent](/press/tenstorrent-selects-sifive-intelligence-x280-for-next-generation1). 

This week also saw the announcement of a new partnership for SiFive, with Renesas licensing the SiFive RISC-V Core IP portfolio and collaborating with us on next-generation RISC-V solutions for the automotive markets. Our product portfolio includes 32 and 64-bit embedded real-time cores; advanced, high-performance RISC-V processor cores; and SiFive Intelligence. We’re excited to see what the future will bring as we collaborate to meet the automotive application requirements and the new AI workloads that will come from it. Read more details on the [Renesas blog post, Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications](https://www.renesas.com/us/en/about/press-room/renesas-and-sifive-partner-jointly-develop-next-generation-high-end-risc-v-solutions-automotive). 

The future of AI processing requires a software-first mindset built on a robust and open ecosystem like RISC-V. We combine RISC-V vectors and SiFive Intelligence Extensions to offer highly power- and memory-efficient compute without sacrificing programmability. RISC-V was invented by the founders of SiFive to build an instruction set architecture for the [new golden era of computing](https://cacm.acm.org/magazines/2019/2/234352-a-new-golden-age-for-computer-architecture/fulltext). The new [SiFive Intelligence line](/cores/intelligence), which is available now, combines all these elements to deliver the flexibility and performance needed by modern AI platforms.

sifiveintelligenceblog04232021.png

## OpenFive Tapes Out SoC for Advanced AI/HPC Solutions on TSMC 5nm Technology

Today, I am pleased to see OpenFive, a SiFive business unit that is the leading provider of customizable, silicon-focused solutions with differentiated IP, is continuing to make progress with AI design solutions with the creation of a reference design chiplet architecture using OpenFive Die-to-Die interface, OpenFive HBM3 IP subsystem, and SiFive 7-Series processor IP, for 2.5D-based SoCs.

The SiFive RISC-V-based processor portfolio is the broadest in the industry, from our upcoming SiFive Intelligence processor cores featuring RISC-V vector capabilities to area-optimized real-time cores. SiFive believes that it takes more than great processor IP to be successful in these markets by offering class-leading advanced trace and debug IP enabled by SiFive Insight. SiFive Insight is delivered pre-integrated with SiFive processor cores and gives customers the tools they need to develop sophisticated applications and is well supported by leading industry tool vendors, IAR Systems, Lauterbach, and SEGGER. Uniquely, SiFive Insight is compatible with Arm® Coresight™ to simplify the use of RISC-V in mixed-ISA environments. 

SiFive addresses security needs with SiFive Shield, a pre-integrated, open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The SiFive Shield hardware cryptographic accelerator optionally enables the necessary elements to accelerate cryptography to securely boot an SoC, protect communications, and restrict access to the debug interface. 

SiFive regularly updates the processor portfolio as part of our ‘relentless innovation’ program, including the SiFive 21G1 release announced recently. You can learn more about the latest features and improvements, including support for half-precision data types for AI applications, [here](https://www.sifive.com/blog/sifive-core-ip-21g1). 

Dr. Chris Lattner, president of engineering and product at SiFive, will present the latest information on SiFive Intelligence at the Linley Virtual Spring Processor Conference on April 23rd. SiFive’s vision is to take a ‘software-first’ approach to SiFive Intelligence products, delivering flexible acceleration strategies that scale with the evolving nature of AI. Find out more and register for the conference, [here](https://www.sifive.com/blog/sifive-intelligence-at-linley-spring). 

AI has created an explosion of diverse architectures, increasing the need for building heterogeneous SoCs and using advanced foundry technology. SiFive and OpenFive IP are proven in TSMC 5nm process technology enabling more choice for leading semiconductor companies to define their next-generation AI-powered products for 5G, automotive, data center, edge, high-performance compute, or networking applications.

sifiveopenfive5nmaisoc.png

## Tremendous progress has been made in the last year bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies. 

SiFive has gone a step further with the inclusion of new vector operations specifically tuned for the acceleration of machine learning operations. These new instructions, integrated with a multicore, Linux-capable, dual-issue microarchitecture, with up to 512b wide vectors, and bundled with TensorFlow Lite support, are well-suited for high-performance, low-power inference applications.

View more about <a href="https://www.sifive.com/cores/intelligence">SiFive Intelligence vector processing software and hardware</a> here.

At the upcoming Linley Spring Processor Conference 2021, Chris Lattner, SiFive’s President of Engineering and Product, will be presenting a technical update on SiFive’s vector processing solutions titled: “Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads.” In his talk, he will demonstrate how SiFive’s integrated software and hardware solution addresses low-power inference applications. Prior to SiFive, Chris led development teams (including TensorFlow infrastructure, MLIR, and other AI work) at Apple, Tesla and Google, and he is the creator of Clang, the compiler front end, as well as LLVM, the compiler infrastructure open source project.

Announced SiFive Intelligence vector processing Core IP includes products capable of supporting full-featured operating systems such as Linux.

We look forward to seeing you at the Linley event and sharing with you the updates to our vector processing solution.


More on SiFive RVV support:

<ul>
<li>SiFive collaborates to support RVV Intrinsics in popular GCC and LLVM compilers (<a href="/blog/risc-v-vector-extension-intrinsic-support">blog</a>)</li>
<li>Extending AI SoC design possibilities through Linux-capable vector processors (<a href="https://www.youtube.com/watch?v=WKNWx232rN4" target="_blank">video</a>)
<li>Introduction to SiFive Intelligence RVV Core IP (<a href="https://riscv.org/news/2020/05/sifive-the-direction-and-magnitude-of-sifive-intelligence-nick-knight-the-linley-group/" target="_blank">video</a>)</li>
</ul>

sifivelinleyapr2021.png

SiFive Vector Processing Solutions To Be Highlighted at Linley Spring Processor Conference 2021

## The best just got better--SiFive’s latest Processor Core IP Portfolio release

We’re pleased to announce a comprehensive update to SiFive’s RISC-V Core IP Portfolio with the SiFive 21G1 release. This release brings important enhancements and new capabilities to SiFive® Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 35% more performance for bit processing algorithms; and up to 25% smaller code size. For a deep dive into the details of this exciting release, register to [watch the webinar on-demand]( /resources/webinar/sifive-21g1-release-webinar). 

## Improved Performance for IoT and AI Applications

There are several key enhancements to SiFive Core IP in the 21G1 release to improve computation throughput, not only through ISA and architecture, but also processor interface connectivity. The SiFive 2-Series and 7-Series processors are now available with the RISC-V “Bit Manipulation” extension, RV32B, with Zba and Zbb extensions. This gives much higher performance in bit processing algorithms, for example Cryptographic Hash algorithm can be accelerated by 35%. 

SiFive processors previously supported double and single precision floating point computation. In the 21G1 release, half precision floating point (FP16) has been added for a more complete floating point computation support. This has been added based on customer needs to reduce memory size and power consumption of floating point computation, as well as use in AI algorithm computation, which uses FP16 extensively. 

## Flexibility in SoC Hardware and Software Integration

This latest release improves SoC implementation of SiFive processors giving more flexibility and options in software programming and hardware connectivity. The organization of the memory map is now fully programmable, where SoC architects can set memory and block positioning to support legacy code or application specific requirements. 

For the U5 Series and U7 Series products (RV64 application processors), virtual addressing up to 48-bits and physical addressing up to 47-bits is supported with the new Sv48 option. This greatly extends the addressing range, allowing the SiFive cores to be easily integrated into large system designs with huge memory requirements. 

In the release, a new ultra low latency, high-bandwidth, interface is added to the 7-series processors, called the Core Local Port. This port is a dedicated interface for each processor, offering direct connectivity. High performance, time critical hardware blocks can be connected directly to the processor, giving low latency throughput, fully deterministic operation for time critical computation. In line with this, SiFive processors now support the new proposed RISC-V NMI specification, for mission critical applications. 

## Higher Performance, Smaller Code size

With the new computation features and data type support in this 21G1 release, high performance is achieved. However a key requirement from SiFive customers is reduction of code size, memory requirements, hence cost. As a result, SiFive has focused on improved libraries and toolchain support. A new and greatly improved C-library that has been fully integrated into the toolchain and SDK allows designers to easily achieve optimum performance, while reducing code size by up to 25% (compared to the previous 20G1 release). 

The processor enhancements in this release increase benchmark performance to 5.18 CoreMarks/MHz and 2.63 Dhrystone/MHz for 7-series processors. 

## Improved Trace, Debug and Security

SiFive Insight is the industry’s first pre-integrated debug and trace IP for RISC-V processor cores, enabling faster silicon bring-up, software/hardware integration, and application development. The Hardware Crypto Accelerator component already within SiFive processors (SiFive Shield) has been further extended with the addition of Public key accelerator (HCA-PKA). 

Uniquely, SiFive Insight features native Arm® CoreSight™ compatibility. By seamlessly integrating with Arm® CoreSight™, developers can integrate SiFive RISC-V based cores into mixed ISA designs and maintain their existing development environment. SiFive Insight has broad industry support from leading software companies such as [Green Hills Software](https://www.ghs.com/news/20200602_RISC-V_tools_support.html), [IAR Systems](https://www.iar.com/products/architectures/risc-v/), [Lauterbach](https://www.lauterbach.com/frames.html?home.html), [SEGGER](https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/), with [SiFive Freedom Studio](https://www.sifive.com/boards) free tools also available. 

With this release, the Trace capability has been greatly enhanced with a variety of new capabilities. The type of tracing (history or branch) is now selectable, as well as the number of communication channels and trace buffer size. The History Trace Messages (HTM) offers 5x compression capability that is recommended for High-Performance multi-core implementations where large amounts of trace data is generated. 

## SiFive’s Best Portfolio Is Here

The SiFive 21G1 release offers new advanced computation capability with bit manipulation packages, half precision floating point, as well as code size reduction by up to 25%. SoC integration in terms of hardware and software has been optimized for more efficient computation, smaller size and faster time to market. 

By using SiFive’s latest release of Core IP, defining and adopting a high-performance, high-efficiency, secure RISC-V processor for your next application or real-time SoC has never been more attractive. Save time and effort with SiFive’s unique support for Arm CoreSight to minimize workflow disruption, and broad tool ecosystem support for SiFive Insight Advanced Trace and Debug. 

We can’t wait to engage with customers on the incredible new devices they’ll build using the substantial new capabilities of the faster, more efficient, more capable than ever SiFive Core IP portfolio. 

Please [contact us](https://www.sifive.com/contact-sales) if you would like to learn more about the SiFive 20G1 release directly from the team, or [watch the webinar on-demand]( /resources/webinar/sifive-21g1-release-webinar). 

**Footnotes 
(1) – 35% improved performance for bit manipulation computation algorithms based on SiFive internal engineering measurement of cryptographic hash function (nettle-sha256) running on a SiFive U7-Series (21G1) processor core. 
(2) – 25% smaller code size with update tools and C-libraries with 21G1 release, in comparison to same toolchain release in 20G1 release. The 25% is the best, largest amount of code size savings. 
(3) – Support for Half precision floating point for a wide range of applications including AI algorithm computation. 
Arm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

21G1 One Slider - Connect.png

**Enabling more choice for Next-Generation Heterogeneous Compute Platforms**

I am excited to see Intel's new [Foundry services business](https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/#gs.wf5uq2) (IFS) in the U.S. and Europe increase the opportunity and choice for the semiconductor industry. We’re pleased to see Intel recognize the utility and opportunity for the RISC-V instruction set architecture in partnering to enable SiFive’s industry-leading Core IP portfolio to enable a new wave of leading-edge technology. 

SiFive is the leading provider of processor cores, accelerators, and SoC IP that technology companies will license to create workload-focused platforms based on the free and open RISC-V specification. While hyperscale computing requirements are increasing and being augmented by decentralized edge datacenters and endpoint on-device processing, the need for IP to power configurable platforms is growing stronger every day. The advantages of SiFive Core IP and the newly added choice of IFS' new business services and leading-edge high-performance capabilities enable our customers to develop these next-generation computing platforms. 

SiFive offers scalable, configurable, silicon-proven RISC-V processor cores pre-integrated with security, advanced trace, and debug features for workload-specific designs. SiFive’s industry-leading portfolio of processor IP scales from Linux-capable high-performance 64-bit multi-core clusters through to power and area-optimized real-time 64-bit and 32-bit cores. Chip designers can use SiFive’s pre-configured standard cores or configure cores optimized for their specific application using the award-winning SiFive Core Designer cloud-based tool. For mission-critical markets, SiFive’s Core IP supports deterministic operation, as described in this [technical paper](https://www.linleygroup.com/uploads/sifive-deterministic-processing-wp.pdf) (PDF) by semiconductor industry analyst, Linley Gwenapp. 

The RISC-V ecosystem is growing rapidly as more leading technology companies invest in RISC-V hardware and software development to secure their technology roadmaps and guide their own future product development. SiFive’s inclusion in the Intel Foundry Services business demonstrates the industry-wide support and adoption of RISC-V, especially in markets seeking high-performance, leading-edge technology. A wide range of software companies and developers are exploring the potential for RISC-V, which was recently demonstrated by running [AWS IoT Greengrass](https://pages.awscloud.com/embeddedworld21.html) on the SiFive HiFive Unmatched developer board, by Aicas. 

SiFive Core IP has been adopted worldwide and is available in products by leading technology companies including ArchiTek, BBC Learning, Coherent Logix, Innovium, FADU, Huami, MicroChip, Synaptics, Qualcomm, and Samsung. SiFive continues to develop new technologies for workload-focused platforms based on open standards to enable higher levels of performance, efficiency, and deeper vertical integration that will enable differentiated computing solutions. Last year, we unveiled the SiFive 20G1 release, and will soon announce the SiFive 21G1 release with new features and improvements as part of our continuous innovation program for our RISC-V IP portfolio. 

Learn more about SiFive processor IP [here](https://www.sifive.com/risc-v-core-ip), and more about the new Intel Foundry Services unit [here](https://www.intel.com/content/www/us/en/foundry/intel-foundry-services.html).

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SiFive collaborates with new Intel Foundry Services to enable innovative new RISC-V computing platforms

*SiFive RISC-V processors are powering flash drives in production as well as addressing emerging In-Storage Computing (ISC) needs*

In the current digital age, where data powers increasing levels of decision-making, industrial control and automation, efficient data storage, movement, and processing become the focal point of technological innovations in silicon, system, and software. At SiFive, we have been designing and optimizing RISC-V based domain-specific solutions to address the challenges of data-centric AI computing. Today, I’m thrilled to share some major progress we’ve made with our customers and partners in storage. 

Storage is always near and dear to the heart of RISC-V, with our good friend, Western Digital, being a strong believer, adopter, and promoter of the technology as well as playing a leadership role in RISC-V International. SiFive’s real-time processor cores had been adopted by storage leaders and innovators from very early on, and we continue to gain a strong foothold in this evolving market. More than 2 years ago in 2018, we announced that [FADU launched](https://www.sifive.com/press/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip) industry-leading SSD solutions powered by SiFive RISC-V Core IP. SiFive’s S51 RISC-V core IP enabled FADU Annapurna controller with 64-bit processing capabilities at ultra-low power and greater efficiency, and according to FADU CEO Jihyo Lee, “SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions, and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.” 

Fast-forward to Nov 2020, at the annual Flash Memory Summit (FMS), FADU announced its [second-generation RISC-V](https://fadutec.com/fadu-technology-announces-delta-ssd-gen4-platform-for-oem-and-hyperscale-data-center-storage/) powered DELTA SSD Gen4 Platform for OEM and hyperscale data center storage powered by SiFive’s S51 RISC-V core IP. FADU captured the honor of being awarded [Best of Show - Most Innovative Flash Memory Startup](https://fadutec.com/fadu-technology-awarded-best-of-show-most-innovative-flash-memory-startup-by-flash-memory-summit-2020/). We are thrilled that the deepened collaboration between FADU and SiFive came to fruition, and we congratulate the entire FADU team for their successful product launch as well as the well-deserved recognition. 

![](https://images.prismic.io/sifive/3af2974c-cab6-42dd-95a0-1a46ab41c6e4_fadussddelta.png?auto=compress,format)

The data-centric AI computing also inspired In-Storage Computing (ISC), another key trend in the storage industry that is aiming to enhance overall computing system efficiency by reducing movement of large amounts of data and processing the data where they are. SiFive has been working closely with InnoGrit Corporation, an emerging leader in advanced storage controllers and smart storage technologies, around leveraging SiFive 7-Series Core IP with both real-time and application processing capabilities as well as the unique SiFive Mix+Match technology to bring computing and intelligence closer to the storage device. The joint effort aims to produce solutions that can reduce I/O processing bottlenecks, enable faster decisions, and deliver more efficient storage utilization in data center and edge applications. 

When InnoGrit and SiFive set forth on this journey together to explore characteristics of storage domain specific processor architecture, we identified a few key features essential for ISC SoC design: 

1. The processor must act as a *responsive front-end processor* to handle essential flash control functions for read and write operations as well as Flash Translation Layer (FTL)
2. The processor also needs to have *application processing capabilities* with Linux support to run data analytics and other data manipulation tasks to increase the share of wallet for SSD controller and future-proof the product for ISC
3. The processor needs to have an *open and non-proprietary architecture* to reduce business risks and enhance product viability at a global scale 

After months of deep technical discussions and evaluation of SiFive’s portfolio of processor Core IP, it became obvious that SiFive’s 7 series RISC-V cores meets the above three requirements beautifully. 
1. SiFive’s E7 and S7 series of high-performance embedded processor cores can deliver low latency and real-time performance to enable fast and efficient data movement, as well as intelligent wear-leveling management to extend the life span and improve the reliability and durability of the SSD storage device.
2. SiFive’s U7 series of silicon-proven and power-efficient application processors can easily run Linux applications to enable various data processing, data analytics, and AI computation to execute within the storage devices itself. SiFive 7-Series Core IP is ideally suited for ISC with options of 32- or 64-bit processing in a silicon-proven package, including SiFive Insight advanced trace and debug, SiFive Shield security and hardware cryptographic accelerator, and integrated platform-level interrupt controller.
3. SiFive’s portfolio of processor Core IP has been built on one consistent, free, and open RISC-V instruction set architecture, invented by the SiFive founders 10 years ago. Development of the RISC-V ISA and extensions is governed by RISC-V International in open working groups composed of technology leaders and leading technology industry company representatives. 

When talking to Dr. Zining Wu, Co-Founder and CEO of InnoGrit Corporation, he told us, “InnoGrit is excited to work closely with SiFive, the leaders and inventors of RISC-V open-architecture, to bring intelligent data processing capabilities to storage devices for the AI Era of computing. We look forward to further integrating data computation and storage functions into InnoGrit ICs with SiFive’s silicon-proven 7 series processor IP that features real-time responsiveness and application workload processing capabilities.” 

Indeed, workload-focused platforms based on SiFive’s 7-Series RISC-V processor architecture enable higher-performance and more efficient data processing for data-centric computing from cloud to the edge. We will continue our technological collaboration with smart storage solution builders like InnoGrit and see RISC-V play an increasingly important role in storage technology evolution. 

Learn more about the latest SiFive 7-Series Core IP updates [here](https://www.sifive.com/blog/the-sifive-20g1-update-for-7-series-core-ip).

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SiFive Strengthens Foothold in Storage Applications for Data-Centric AI Computing

## Creating a RISC-V PC Ecosystem for Linux application development

Today, SiFive introduces the new HiFive platform for professional RISC-V developers, the HiFive Unmatched! The HiFive Unmatched enables developers to create the RISC-V-based software they need for RISC-V platforms. From real-time operating systems to custom Linux distributions, and the compilers, libraries, and applications that go with product design, developers can use the HiFive Unmatched to natively test and build RISC-V code. 

![SiFive HiFive Unmatched](https://images.prismic.io/sifive/22f77781-c477-44a0-950f-f14a099d8ad9_unmatched-board.png?auto=compress,format)

At the heart of the SiFive HiFive Unmatched board is the new SiFive FU740 SoC, a five-core heterogeneous, coherent processor with four SiFive U74 cores, and one SiFive S7 core. If you’ve been following SiFive for a while, you’ll know that the U-Series are SiFive’s Linux-capable 64-bit application processor cores, based on the RISC-V ISA that the founders of SiFive invented. SiFive S-Series cores are 64-bit real-time embedded cores designed to enable mission critical or deterministic processing. Combined in the SiFive FU740 using SiFive Mix+Match technology, the heterogeneous multicore complex offers a potent combination of application and real-time processing. You can learn more about the latest features and capabilities of SiFive 7-Series Core IP, [here](https://www.sifive.com/blog/the-sifive-20g1-update-for-7-series-core-ip). 

The SiFive HiFive Unmatched comes in the mini-ITX standard form factor to make it easy to build a RISC-V PC. For the first time, standard industry connectors such as ATX power supplies, PCI-Express(r) expansion, Gigabit Ethernet, and USB ports are present on a single-board RISC-V development system. 

The HiFive Unmatched includes 8GB of DDR4 memory, 32MB of QSPI flash memory, and a microSD card slot on the motherboard. For debugging and monitoring, developers can access the console output of the board through the built-in microUSB type-B connector. 

Expansion is simple with the onboard PCI-Express slots, including both a PCIe general purpose slot (PCIe Gen 3 x8) for graphics, FPGAs, or other accelerators; and, M.2 slots for NVME storage (PCIe Gen 3 x4) and Wi-Fi/Bluetooth modules (PCIe Gen 3 x1). Additionally, there are four USB 3.2 Gen 1 type A ports on the rear, next to the Gigabit Ethernet port, making it easy to connect your peripherals. 

The system will be shipped with a bootable SD card that includes Linux and popular system developer packages, with updates available for download from SiFive.com. From regression testing farms to individual developer contributions to the maturing RISC-V open software ecosystem, the SiFive HiFive Unmatched makes building exciting new applications and products more accessible than ever before. Priced at $665USD (suggested retail price), the system will be available for pre-order soon; please contact us [here](https://www.sifive.com/boards/hifive-unmatched) to register your interest.

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The Heart of RISC-V Development is Unmatched

## Faster, More Efficient SiFive 7-Series Core IP

Today, we’re announcing the SiFive 20G1 6.0 update, which is focused on improving the 7-Series line of products. Our previous release, SiFive 20G1, was a comprehensive update that spanned from the 7-Series to the 2-Series, including U-, S-, and E-Cores. Similarly, the 20G1 6.0 update improves the performance, features, and functionality of SiFive 7-Series U-, S-, and E-Cores. 

Ever since the 7-Series [introduction](https://www.sifive.com/press/sifive-core-ip-7-series-creates-new-class-of-embedded) in 2018, SiFive has been able to bring advanced compute capabilities to embedded, industrial, and storage markets. These markets require high-performance compute in constrained thermal environments while being able to maintain real-time service guarantees. In addition, they also require access to stable software stacks providing functionality for Human Machine Interface (HMI), real-time control, and rich connectivity.

The SiFive 7-Series RISC-V processor cores can address all of these requirements. The 7-Series offers high-performance, multi-core compute, while still being extremely energy efficient. The 7-Series has many capabilities which make it suitable for real-time applications, and these real-time features apply across the 7-Series range: both the E7 and S7 Embedded cores as well as the U7 Application Cores. The 7-Series can scale to heterogeneous multi-core compute architectures via SiFive Mix+Match capabilities, allowing for a coherent mix of SiFive U- and S- cores in the same core complex complete with SiFive Insight Advanced Trace and Debug, SiFive Shield security, single 64-bit memory map, and interrupt controllers. These are all pre-integrated and verified in a single IP deliverable to save you time and engineering resources. And most importantly, the SiFive 7-Series is built on the open-source RISC-V ISA, bringing compatibility with the industry's fastest growing ecosystem. 

The 20G1 6.0 update builds on the improvements in the 20G1 release to enhance the capabilities of the 7-Series by further increasing performance and efficiency and adding features. Join Dany Nativel and me as we host a webinar showcasing these new improvements. We’ll also feature guest speaker, Jeff Hancock, a product manager at Mentor Graphics, who’ll talk about the latest Real-Time Operating System (RTOS) offering from Mentor, [Nucleus 4](https://www.mentor.com/embedded-software/nucleus/), which brings support for SiFive and RISC-V. He’ll also cover the importance of deterministic software and hardware for mission-critical markets.

[Register](https://www.sifive.com/resources/webinar/the-sifive-7-series-is-now-available-with-more-performance) for the webinar, and [sign up](https://info.sifive.com/sifive-newsletter-signup) for our newsletter to be notified of an new technical paper written by Linley Gwenapp, Principal Analyst for The Linley Group, on determinism and mission-critical applications.




The SiFive 20G1 Update for 7-Series Core IP

## A note from SiFive President & CEO, Patrick Little 

I’m honored to join SiFive to lead the brilliant, hard-working team of innovators and engineers who are responsible for creating some of the most impactful architectures in the technology industry. Ten years ago, an inspired team of computer scientists set out to invent a better way for hardware and software to talk to each other, free of legacy overhead and unencumbered by complexity, bringing the RISC-V Instruction Set Architecture to life. 

Five years later, encouraged by worldwide grassroots support, that same team launched SiFive and the RISC-V International organization, creating an inclusive and truly open business model for the technology industry to solve their computing challenges. RISC-V International is comprised of leading technology companies and scientists, enabling member companies and individual contributors to openly collaborate on the development and extension of the ISA. 

I’m just beginning to get to know the team and I’m immediately impressed by the passionate culture of SiFive, extending a warm welcome and demonstrating a rare energy of innovation and excellence that I’m excited to become a part of. Over the coming quarter, we’ll get to know each other better as we accelerate into the next phase of growth for the company, leveraging the inflection point that has coincided with my decision to join SiFive. 

**The Moment Is Now** 
Across the technology industry, a sharpened focus on workload-acceleration to solve next-generation computing challenges is driving demand for SiFive’s configurable RISC-V-based platforms. The industry wants choice in an open and free market that grants them control over their roadmaps, features, and partners; a choice that SiFive offers. 

I’m excited to see the increase in focus on SiFive’s industry-leading RISC-V-based portfolio. SiFive continues to drive the adoption of RISC-V for application and embedded designs, using our portfolio of configurable RISC-V-based microarchitectures with unique features such as pre-integrated security and advanced trace and debug capabilities, and the ability to mix and match cores in a heterogenous complex. We support this with a software and tool package to create a platform our customers can use to drive their own success. 

**Investing In The Roadmap** 
We’ll also continue to work hard on bringing our next-generation processor architectures to market, including the upcoming SiFive Intelligence processor architecture that tightly integrates vector capabilities into the scalar processor core. This tightly-integrated core, using a single ISA, enables a range of solutions for intense computational challenges, from deep learning in the data center to image, video, or audio processing at the edge. 

We’ll have more details on this at the Linley Group Fall Virtual Processor Conference, where Dr. Krste Asanovic, RISC-V co-inventor, SiFive co-founder and Chief Architect, will give a deep dive on the platform. 

To further enable professional developers, SiFive will launch a new HiFive board this year, to stand alongside the [Microchip PolarFire SoC](https://www.crowdsupply.com/microchip/polarfire-soc-icicle-kit) for developing RISC-V applications and solutions. The new SiFive HiFive board will be based on the upcoming SiFive FU740 SoC, details of which Dr. Yunsup Lee, RISC-V co-inventor, SiFive co-founder and Chief Technology Officer, will present at the Linley Group Fall Virtual Processor Conference. You can learn more about SiFive's presence at the conference [here](https://www.sifive.com/press/sifive-to-introduce-new-risc-v-processor-architecture). 

**What’s Your RISC-V Strategy?** 
Across the industry, technology and semiconductor companies are constantly evaluating the best new platform choice for their next-generation products. SiFive’s industry-leading RISC-V technology portfolio, combined with the talent and passion of this team, provides what we need to enable solutions for the workload-focused challenges of our customers to be successful. 

SiFive has consistently had a wide range of market opportunities and that is true now more than ever. We’re ready to work hard, identify the best customer opportunities, and build the products that will enable the most amazing new experiences in the industry. Let’s go change the world, SiFive!!! 

- Patrick

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## Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive.

As an aspect of entropy, randomness enables the generation of cryptographic methods to protect data, chips, and systems. By harnessing the nature of randomness as the basis of a secure system, it is possible to enhance the security of computer systems and protect vital information. 

In July, SiFive introduced the SiFive Shield hardware cryptographic accelerator (HCA), as part of the improvements contained in the SiFive 20G1 release. The SiFive Shield HCA block consists of the necessary elements to accelerate cryptography to securely boot an SoC, protect communications, and restrict access to the debug interface. 

I’m pleased to share with you that the SiFive HCA IP block includes a 100% digital true random number generator (TRNG) that has successfully passed a conformance evaluation against the stringent NIST SP-800-90B recommendation for entropy sources used for random bit generation. 

The SiFive HCA TRNG is a fully-digital IP block that offers customization options for the entropy source, including customization of the entropy rate. SiFive’s selected independent partner, 
Penumbra Security, Inc. (Penumbra) is a NVLAP-accredited Cryptographic and Security Testing laboratory under the Cryptographic Module Validation Program (CMVP) at National Institute of Standards and Technology (NIST). 

Happily, Penumbra asserts that SiFive’s method of customizing the entropy rate is effective, and demonstrated targeted entropy rates between 64.9% entropy and 92.4% entropy with the predicted entropy rates aligning with the actual entropy rates. Once integrated, the TRNG can be evaluated and certified against NIST SP-800-90C standard since through an additional SP-800-90A conditioning step enabled via SiFive software library that leverages the SiFive HCA hardware SHA/AES. 

The SiFive HCA block can be added into SiFive RISC-V processor cores, alongside other SiFive Shield components such as SiFive WorldGuard. SiFive WorldGuard enables true multi-domain security with multiple hardware enforced domains available for securely processing data across the whole SoC, even in multi-core designs with many primary bus controllers. SiFive Shield is portable and scalable with broad process technology support to ensure consistency over time. 

The SiFive 20G1 release with SiFive HCA block is available now. You can read more about the SiFive 20G1 release in our blog, [here](https://www.sifive.com/blog/sifive-core-ip-20g1).

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Randomness is Secure with SiFive Shield HCA

## The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. 

The RISC-V International vector working group is composed of experts from industry and academia, to create a standard extension that can be ratified for general adoption among any who choose to adopt RVV. 

We’re incredibly pleased to announce that a team from SiFive and the Barcelona Supercomputing Center have collaborated to create a new API to support RISC-V Vector Intrinsics in popular compilers, GCC and LLVM. The API is available now on GitHub, [here](https://github.com/riscv/rvv-intrinsic-doc). 

As RISC-V continues to work towards ratification of the final version of the RISC-V Vector Extension, support will continue to be updated and added to create an industry-wide tool chain to enable widespread adoption of vector processing based on RISC-V. 

We have implemented the majority of the API in GCC to validate the currently proposed 1.0 specification. In addition to the RISC-V Vector specification, we have also implemented support for scalar and vector FP16 (Zfh), atomics (Zvamo), and segmented load/store (Zvlsseg) intrinsics. Full support of the currently proposed 1.0 specification has been implemented in the assembler. 

The team has integrated RVV intrinsics into risc-gnu-toolchain, so you can build the intrinsic enabled GNU toolchain as usual. We’ve also verified using our internal test suite and a few internal projects. We have extensively tested the intrinsics and our teams have used the intrinsics to implement different vector algorithms to help validate the vector implementation. 

In the near future, RISC-V Vector intrinsics will be implemented in the LLVM compiler and the work will be submitted upstream. This announcement also serves as a call-to-arms for the RISC-V community, to review and assist as we update the current implementation to the latest RISC-V Vector 1.0 draft specification. 

The hardware and software teams at SiFive are hard at work on SiFive Intelligence, our range of processor IP featuring RISC-V cores with vector capabilities. We’ll have more details on these cores later this year. Until then, we’re excited for the progress being made on building the ecosystem for converged processor cores that include scalable vector capabilities, to help design the domain-specific computing solutions needed for today’s computing challenges. 

Domain-specific architectures based on open standards enable deeper levels of performance, efficiency, and vertical integration to provide differentiated computing solutions. The focus of SiFive IP business unit is creating incredible processor core architectures that take a step forward from general purpose CPUs and GPUs housed together in a system, to a deeper level of compute convergence. The industry-wide interest and support for RISC-V Vector extensions is a great indicator of the potential of SiFive Intelligence.

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RISC-V Vector Extension Intrinsic Support

## OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs

Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. 

![OpenFive Custom Silicon Business Unit](https://images.prismic.io/sifive/1881cd91-fe60-4f34-acd8-af7b37a3c13a_Openfive.png?auto=compress,format)

The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of [Dennard scaling](https://ieeexplore.ieee.org/document/9162812), general purpose processors have become very power hungry and performance increases are hard to find from process technology alone - architecture plays a key role in workload acceleration. 

We’re not alone in seeing this opportunity, as leading technology companies are embracing domain-specific accelerators targeted for applications such as AI training/inference, network virtualization and computational storage. Domain-specific or workload-focused silicon enable the cost-effective, scalable products desired by technology companies who want to own their roadmap and vertically integrate their products with hardware and software IP. 

OpenFive is built around a balance of silicon expertise and customizable IP, including a focused portfolio of SoC IP to enable key design features. OpenFive’s advanced design methodologies enable the use of leading edge foundry nodes, including 5nm, with 2.5D packaging technology, to build Artificial Intelligence, Edge Computing, HPC, and Networking solutions. 

The OpenFive IP portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory (HBM2/E), USB subsystem IP, and die-to-die interconnect IP for next-generation heterogeneous chiplet-style products. OpenFive’s broad industry expertise enables us to develop SoCs with a variety of processor cores, including RISC-V ISA as well as processors from Arm, Cadence, CEVA, and Synopsys. 

This ISA-agnostic and open approach will help accelerate the adoption of RISC-V in new designs, as chip designers look for the best IP for each functional block inside their SoC designs. The open, free RISC-V ISA is the basis for the SiFive Core IP portfolio - the broadest in the industry. SiFive cores, along with other RISC-V based cores, and cores from other ISAs, can make a heterogeneous mix of application, embedded, and microcontrollers to enable a modern domain-specific design. 

We’re incredibly excited about the opportunity that domain-specific silicon offers OpenFive customers in their next-generation products. With a heritage and expertise spanning more than 15 years, over 150M units shipped, and more than 350 tape-outs, OpenFive’s end-to-end expertise in Architecture, Design Implementation, Software, Silicon Validation and Manufacturing enable the design and delivery of high-quality silicon, with first-time-right results. 

For more information on the portfolio of IP and silicon solutions OpenFive can provide for your new vertically-integrated, differentiated design project, please connect with us [here](https://www.sifive.com/contact-sales). 

*All trademarks referenced herein belong to their respective companies.*

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OpenFive's Customizable Silicon-Focused Solutions

## SiFive's Best Processor Portfolio Is Here

We’re pleased to announce a comprehensive update to SiFive’s RISC-V IP Portfolio with the SiFive 20G1 release. This release brings important enhancements and new capabilities to SiFive Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ultra-capable SiFive U7-Series to the extremely popular SiFive E2-Series, offering up to 2.8x more performance(1); up to 25% lower power(2); and up to 11% smaller area(3). 

## Setting the Standard for RISC-V Cores

SiFive offers processor cores based on the free and open RISC-V ISA - after all, SiFive was founded by the inventors of RISC-V. The mission of SiFive is to enable the development of domain-specific silicon, and market feedback combined with SiFive customer experience tells us that a processor core must include all of the necessary components to integrate, secure, and develop software for the CPU core - [SiFive Shield](https://www.sifive.com/blog/sifive-shield-an-open-scalable-platform-architecture), and [SiFive Insight](https://www.sifive.com/soc-ip/sifive-insight). 


## Accelerating Product Development

SiFive Insight is the industry’s first pre-integrated debug and trace IP for RISC-V processor cores, enabling faster silicon bring-up, software/hardware integration, and application development. 

Uniquely, SiFive Insight features native Arm® CoreSight™ compatibility. By seamlessly integrating with Arm® CoreSight™, developers can integrate SiFive RISC-V based cores into mixed ISA designs and maintain their existing development environment. SiFive Insight has broad industry support from leading software companies such as [Green Hills Software](https://www.ghs.com/news/20200602_RISC-V_tools_support.html), [IAR Systems](https://www.iar.com/products/architectures/risc-v/), [Lauterbach](https://www.lauterbach.com/frames.html?home.html), [SEGGER](https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/), with [SiFive Freedom Studio](https://www.sifive.com/boards) free tools also available. 

## High-Performance, High-Efficiency Processor Cores 

There are several key enhancements to SiFive Core IP in the SiFive 20G1 release to improve power, performance, and area (PPA). Enhancements to the high-performance U7-Series application processor have reduced power consumption by more than 25%(2), while increasing load bandwidth up to 2.8x for streaming data applications such as those in AI Acceleration applications(1). 

![SiFive Core IP 20G1 Update PPA vs 19.08](https://images.prismic.io/sifive/fdd45650-2fa9-447d-ab1a-308b16eebf70_072220-SiFive-CoreIP-20G1-PPA-Blog.png?auto=compress,format)

The SiFive E3- and E7-Series are now available with the RISC-V “Embedded” extension, RV32E, delivering an area reduction of up to 11%(3) compared to RV32I to further improve PPA for these cores. Based on customer feedback, RV32E will be a very popular option for product designers who need area-constrained high-performance embedded CPUs. The SiFive 3-, 5-, and 7-Series cores have been refreshed with new, enhanced real-time capabilities, bringing deterministic performance for high-reliability designs to SiFive’s winning product portfolio. 

SiFive’s advanced platform engineering expertise enables our roadmap development to be quickly integrated and validated on FPGAs to rapidly test improvements and new features of our product line. SiFive includes FPGA bitstreams in customer packages to enable high-performance software-development platforms, now including the [VCU118](https://www.xilinx.com/products/boards-and-kits/vcu118.html) based on the Xilinx UltraScale+ family of FPGAs, offering a software development platform for the entire SiFive Core IP portfolio including large multi-core configurations. 

## Processor Optimization 

The [award-winning](https://www.elektraawards.co.uk/elektraawards2020/en/page/2019-winners) [SiFive Core Designer](https://www.sifive.com/core-designer) cloud-based development application for configuring your own processor core ties the SiFive 20G1 release together, making SiFive Core IP simple and easy to work with. In the SiFive 20G1 release, we adopt a new version scheme by moving from “year/month” naming to “year/release.” The SiFive 20G1 release is the first General Release of 2020, and encapsulates 9 months of hard work and progress at SiFive as we move to a new release schedule driven by our roadmaps and aligned to customer engineering cycles. SiFive Core Designer allows chip-designers to fine-tune a SiFive processor to meet their workload requirements, selecting which features and functionality are required. 

## Building Secure SoCs

SiFive Shield, an open, scalable platform architecture designed to enable whole SoC security for RISC-V, is pre-integrated into SiFive Core IP and configured via SiFive Core Designer. Freshly added in the SiFive 20G1 release is support for the SiFive Shield Hardware Cryptographic Accelerator (HCA) IP add-on option. 
SiFive HCA IP offers a configurable mix of AES, SHA, and TRNG functions to enable secure Root of Trust and hardware-accelerated cryptographic functions. SiFive Shield HCA is configured using SiFive Core Designer and is pre-integrated and verified along with SiFive Core IP deliverables, including accompanying documentation, software, and drivers. 

## Making Great Applications

In software discussions, one of the first questions we get asked is about the FreeRTOS™ real-time operating system. FreeRTOS support for RISC-V was integrated into the official FreeRTOS releases in early 2019, and the SiFive Freedom E SDK now includes FreeRTOS v.10, with source code and build scripts integrated into the SDK. Alongside the FreeRTOS kernel, the SiFive Freedom E SDK features several FreeRTOS-based examples, including using Physical Memory Protection (PMP) to enable secure runtime operations. 

The SiFive Freedom E SDK board support packages (BSP) have been upgraded to include System View Description (SVD) files, bringing tighter integration into debug environments. 

![SiFive Freedom Studio](https://images.prismic.io/sifive/407ea7f6-8469-4952-9a91-af5595089668_sifive-insight-traceview.png?auto=compress,format)

[SiFive Freedom Studio](https://www.sifive.com/boards) enables faster development of new products through enhanced support for SiFive Insight Advanced Trace and Debug including new views of trace flow to speed up debugging.

## SiFive’s Best Portfolio Is Here

The SiFive 20G1 release offers impressive PPA improvements combined with new pre-integrated SiFive Insight trace and debug to save time and effort with SiFive’s unique support for Arm® CoreSight™ to minimize workflow disruption, and broad tool ecosystem support. Defining and adopting a high-performance, high-efficiency, secure RISC-V processor using SiFive Shield security features and add-on options for your next application or real-time SoC has never been more attractive with SiFive. 

We can’t wait to engage with customers on the incredible new devices they’ll build using the substantial new capabilities of the faster, more efficient, more capable than ever SiFive Core IP portfolio. 

Please [contact us](https://www.sifive.com/contact-sales) if you would like to learn more about the SiFive 20G1 release directly from the team. 

**Footnotes 
(1) – 2.8x higher performance based on SiFive internal engineering measurement of improving performance in memory-intensive workloads running on a SiFive U7-Series processor core; when normalized the SiFive U7-Series processor (19.08) offers 36% of the performance of the SiFive U7-Series processor (20G1). 
(2) – 25% lower power based on SiFive internal engineering measurement of SiFive U74 processor (20G1) core power consumed while running Dhrystone benchmark as compared to SiFive U74 processor (19.08); when normalized the SiFive U74 (19.08) processor offers 133% of the power consumption of the SiFive U74 (20G1) processor. 
(3) – 11% area reduction based on SiFive internal engineering measurement of SiFive E3-Series area using RISC-V Embedded extension RV32E in 28nm process technology vs. RV32I; when normalized the SiFive E3-Series (19.08) measures 112% larger area of the SiFive E3-Series (20G1), using 28nm process technology. 
Arm and CoreSight are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

072220-SiFive-CoreIP-20G1-PPA-LI.png

## A Message From The CEO

Innovation in SiFive’s product portfolio and business model differentiates our company, but the employee team is the heart of our success. SiFive employees enable our company to offer the full idea-to-silicon journey, from configurable processor cores with comprehensive pre-integrated security, trace and debug capabilities, and modern SoC IP, to scalable chip manufacturing development and management using a broad range of foundries and process technologies. 
 
To support the areas that SiFive employees live in, we will be making charitable donations to local communities around our design centers. We value our employee’s health and safety, and our commitment to keeping them and their families safe during this time is a top priority. 

Recently, SiFive announced our participation in the [COVID-19 pledge](https://opencovidpledge.org/), and we now offer the [SiFive E21](https://www.sifive.com/cores/e21) processor core IP [free](https://opencovidpledge.org/license/v1-0/)* to help those creating solutions to healthcare issues created by the pandemic. We encourage our partners and customers to continue to find ways to positively contribute to potential solutions for the challenges caused by COVID-19. For more information on using the SiFive E21 standard core IP in a design under the terms of the COVI-19 pledge, please contact our [sales team](https://www.sifive.com/contact-sales). 

SiFive’s mission is to make the idea-to-silicon journey easier, helping startups and established companies alike to solve the computing challenges they face. To achieve this goal, SiFive focuses on offering excellence, engineering, and expertise to enable customer domain-specific silicon. This focus was a key element in my decision to join SiFive, guiding and growing operations and programs to develop innovative solutions for computing challenges. 

A key element in this approach is SiFive’s innovative processor IP and scalable platform engineering methodology combined with a forward-thinking business model. SiFive was founded on the principle of using open standards to develop efficient, high-performance, SoCs with methodologies based on scalable reuse. To that end, SiFive offers a licensing and use model that does not require upfront IP licensing costs. Industry partners have joined in this model through SiFive’s [DesignShare](https://www.sifive.com/designshare) program. 

With flexible support and engineering engagement available to support customer core and silicon development, SiFive’s approach enabled scaling to a global presence quickly. SiFive’s sixteen design centers around the globe coupled with decentralized infrastructure and web-based products such as SiFive Core Designer continue to deliver on our customer commitments. 

Keep in touch with SiFive via our social media channels to follow the latest developments as we continue to support our local communities, create great technology, and free semiconductor roadmaps. 


* *The SiFive E21 Standard Core is offered under the [Open COVID license 1.0](https://opencovidpledge.org/license/v1-0/).

message-from-CEO.jpg

Published by [SemiWiki](https://semiwiki.com/ip/sifive/285092-sifives-approach-to-embedding-intelligence-everywhere/).


Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made over many years.  RISC-V was conceived with a clean well-thought-out architecture and designed for expansion that would not create inconsistencies. Because it is open source, there is a rich set of tools and products that support it.

SiFive is one of the leading exponents of RISC-V and has been producing IP based on the RISC-V ISA for years now. Their product offerings have expanded significantly, now addressing everything from edge/IoT to server applications. Their recent webinar titled “Embedding Intelligence Everywhere with SiFive 7 Series Core IP” talks about how intelligence is needed in each market.

![Embedding Intelligence Everywhere](https://images.prismic.io/sifive/11123394-15b6-406a-bad5-c6483df27170_embedding-intelligence-everywhere-blog.jpg?auto=compress,format)

The webinar is divided into two parts. The first, presented by Jack Kang, Senior Vice President of Customer Experience at SiFive, offers a look at how embedded intelligence is becoming prevalent everywhere from the cloud to the edge. He also offers an overview of SiFive’s embedded RISC processors and how they fit current market needs.

Jack first talks about how AI is moving from the cloud to the edge, creating the need for additional processing capabilities in a wide range of devices. At the edge AR, VR and sensor fusion are driving the need for expanded real time processing. Jack also points out that there is also a need for increased intelligence in storage. He touches on how intelligence is supporting caching schemes, cryptography, memory maps and even in-cluster application processors. Likewise, making networking smarter facilitates higher bandwidth and other activities such as the implementation of 5G stacks.

The cores offered by SiFive are grouped by their application areas. The E Cores are suitable for 32-bit embedded uses. For heavier workloads there are the S Cores, which add 64 bit capabilities. The most powerful processors are the U Cores, which are 64-bit application processors for high-end computing.

Their smallest and most efficient RISC-V processor IP is the 2 Series, the E2 and S2, which are 32 and 64 bit respectively. They are core and memory configurable to customer specific needs. They also feature ultra-low latency interrupts for servicing real world events.

The 3 and 5 Series are their most widely deployed products. The E3 offers 32 bit performance for mid-range embedded applications. The S5 adds 64 bit and the U5 is the top end offering higher performance. These cores can be used in multicore configurations and have Hard Real Time capabilities.

The 7 Series cores are the topic of the later second section of the webinar. Jack touches on them before talking about the U8, an extremely scalable high performance out-of-order core with their highest performance per watt. The U8 is also very area efficient. The combination of area and power efficiency make them very attractive for high end computing systems.

The second section, presented by Jahoor Vohra, Director of Field Application Engineering, is titled “SiFive 7 Series Core IP”. His presentation discusses the features of the three members of the Core IP 7 Series: E7, S7 and U7. This includes an overview of the 7 Series microarchitecture, focusing on performance, scalability and the detailed specifications of each.

The 7 Series are scalable up to 8+1 for each cluster. Like other RISC-V processors the instruction set is extensible through custom instructions. Their memory is configurable and tightly integrated for low latency. If called for, they support mixed precision arithmetic. They also feature enhanced determinism to better support demanding real time applications. There are also functional safety features provided by built-in fault tolerance mechanisms. These are just a few of the highlights that Jahoor brings up.

To gain a full appreciation and understanding of the SiFive offerings, across the board and about the 7 Series in particular, I highly suggest viewing the [informative webinar](https://www.sifive.com/resources/webinar/embedding-intelligence-everywhere-with-sifive-7-series). I have been following RISC-V and SiFive for a number of years now. The level of adoption and progress has been extraordinary. The entire effort is supported by some brilliant dedicated minds. The results speak for themselves.

SiFive is also giving a webinar soon on the topic of Rapid Embedded Prototyping with SiFive Software [see details](https://info.sifive.com/rapid-embedded-prototyping-with-sifive-software). These webinars are all part of the SiFive Connect webinar series, which aims to provide educational content in an interactive format. A full list of these webinars can be found [here](https://www.sifive.com/resources/webinars).


SiFive’s Approach to Embedding Intelligence Everywhere

A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions.

After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the globe and is here to stay. RISC-V cores are being designed into many SoCs and domain-specific custom silicon. To take our previous engagement with the global community to the next level, we’re launching the SiFive Connect Webinar Series as a highly educational and interactive platform for SoC developers to connect directly, on an ongoing basis, with industry experts. Targeted for engineers, architects, developers, researchers and students, attendees will learn about the RISC-V ecosystem and the latest RISC-V based cores and software, security solutions, SoC and system IP, various end market solutions and development platforms. 

These bimonthly webinars will be one hour in duration, and each will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT – enabling the global community to choose the time that works best for them.

Registration is now open for the first two SiFive Connect webinars of 2020!
- Thursday, April 16, 2020 
![Embedding Intelligence Everywhere](https://images.prismic.io/sifive/02667a10-9df0-478c-9099-7451cbe31b8d_embedding-intelligence-blog-photo.jpg?auto=compress,format)
Embedding Intelligence Everywhere with SiFive 7 Series Core IP 
[View Abstract & Register to Attend](https://info.sifive.com/embedding-intelligence-everywhere-with-sifive-7-series-core-ip)

- Thursday, April 30, 2020 
![Rapid Embedded Prototyping with SiFive Software](https://images.prismic.io/sifive/8ced59ef-f22b-4e4a-8aa4-66ee6260d127_rapid-embedded-prototyping-blog-photo.jpg?auto=compress,format)
Rapid Embedded Prototyping with SiFive Software 
[View Abstract & Register to Attend](https://info.sifive.com/rapid-embedded-prototyping-with-sifive-software)

To view an extended list of upcoming topics, please visit [www.sifive.com/resources/webinars](https://www.sifive.com/resources/webinars).

We look forward to engaging with you and sharing knowledge!

SiFive Connect : SiFive in Virtual World-Webinar Series

## The SiFive Mission

SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips designed to solve a focused problem with built-in adaptability to provide flexibility for shifting workloads. 

![](https://images.prismic.io/sifive/09ae0aeb-c69f-4a46-871d-02ef15936a07_SiFiveIdeaToSiliconsm.png?auto=compress,format)
Today, [Synopsys announced](https://news.synopsys.com/2020-03-25-SiFive-Selects-Synopsys-Fusion-Design-Platform-and-Verification-Continuum-Platform-to-Enable-Rapid-SoC-Design) that SiFive has selected Synopsys Fusion Design Platform™ and Verification Continuum™ to further enable SiFive’s vision of rapid cloud-based design. SiFive will leverage Microsoft Azure to power our portfolio of design tools, enabling [SiFive platform engineering](https://www.sifive.com/blog/with-sifive-we-can-change-the-world) to continue to scale and deliver high-quality IP and solutions for customer challenges. 

With 16 design centers across the globe, SiFive leverages global collaboration tools to complete our work. And where those tools don’t exist, or need to be more efficient, [we build them](https://www.youtube.com/watch?v=L7L2r4Tp2J0). Scalable chip design can be abstracted to a compiler and language problem, once you have established the parameters for interfaces on your SoC IP building blocks. With pre-integrated IP, scalable building blocks, and the power of cloud-based tools, silicon at the speed of software becomes a reality. 

One popular example accelerator is machine learning inference; different inference processing models have different hardware design requirements. The market for deep learning accelerators is growing, as the global deep learning market is [expected to grow](https://www.globenewswire.com/en/news-release/2020/01/27/1975409/0/en/Deep-Learning-Market-Size-Worth-US-56-427-2-Mn-By-2026.html) at a CAGR of 51.1%, reaching a market value of over $56B US by 2026. Further [forecasts show IoT growth](https://www.gartner.com/en/newsroom/press-releases/2018-11-07-gartner-identifies-top-10-strategic-iot-technologies-and-trends) reaching 25 billion devices by 2021 from the 2019 level of 14.2 billion. To reduce anticipated network pressure, data can be processed and decisions made at the edge or endpoint device. 

On-device decisions drive new design requirements for the core, cache, memory, and processing offload accelerators used inside the silicon. An agile, scalable, programmatic approach to SoC design is required to create domain-specific accelerators and bring them to market quickly. 

SiFive Core IP enables processor cores to be generated, based on standard core definitions in our product range with configurable options. [SiFive Core Designer](https://www.sifive.com/core-designer) is an [award-winning](https://www.elektraawards.co.uk/elektraawards2019/en/page/2019-winners) web-based tool for silicon engineers to quickly configure SiFive RISC-V based cores, leveraging the broad SiFive Core IP portfolio. This is enabled through the use of programmatic techniques for integrating IP and creating core derivatives using generators. In 2018, we proved the efficacy of the solution by using these techniques and tools to create an SoC in just 6 months, from concept to booting Linux. 

Using a fully cloud-based methodology, SiFive [taped out](https://www.design-reuse.com/news/44851/tsmc-oip-ecosystem-enabled-in-the-cloud.html) the SiFive Freedom Unleashed FU540 64-bit RISC-V Linux chip and presented the results at the 2019 Design Automation Conference in Las Vegas. The SoC features a SiFive U54 multicore complex plus interconnects for accelerators, high-speed I/O, and DDR3/4 memory. 

The next level is the ability to rapidly enable new designs focused on domain-specific workloads. Shubu Mukherjee, SiFive Chief SoC Architect published a blog series on domain-specific accelerator (DSA) designs with SiFive RISC-V-based SoCs([1](https://www.sifive.com/blog/part-1-fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v),[2](https://www.sifive.com/blog/part-2-high-bandwidth-core-access-to-accelerators-enabling-optimized-data-transfers-with-risc-v),[3](https://www.sifive.com/blog/part-3-high-bandwidth-accelerator-access-to-memory-enabling-optimized-data-transfers-with-risc-v),[4](https://www.sifive.com/blog/part-4-high-performance-interconnect-for-accelerators-enabling-optimized-data-transfers-with-risc-v)). Achieving rapid DSA enablement requires scaling the programmatic approach to core design to the whole SoC, leveraging high-quality cloud-based tools. 

SiFive’s mission is to reduce the time, complexity and cost of custom silicon for people trying to solve today’s computing challenges. Today, we continue to scale our enablement of the idea to silicon process that will drive silicon at the speed of software. With SiFive, you can unleash your roadmap and declare silicon independence.

SiFiveIdeaToSilicon.png

## Access, Observe, Control

The term ‘debug’ has a storied history. It’s [widely reported](https://www.computerworld.com/article/2515435/moth-in-the-machine--debugging-the-origins-of--bug-.html) as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison, from a letter he wrote in 1878. Whatever the origin, we all agree that we don’t want bugs in our systems, our hardware, our code. 

With computer systems long past the size where physical inspection is feasible, and programming using wires or punch cards long gone, we need new methods. We need insight into the machine, the code, the operations happening millions of times per second right in front of us to create high-quality products, accurately and quickly. 

*An Industry Leading RISC-V Trace & Debug Portfolio* 

Today, SiFive are pleased to announce [SiFive Insight](https://www.sifive.com/technology/sifive-insight), a portfolio of trace and debug IP, software, and tools, to make the development of new SiFive RISC-V products efficient and simple. Observing product operation is critical for developing secure, efficient systems. These trace and debug features allow access to system state information, and even modification, to better understand the system’s operational flow. 

![SiFive Insight Trace Operation](https://images.prismic.io/sifive/407ea7f6-8469-4952-9a91-af5595089668_sifive-insight-traceview.png?auto=compress,format)

The capability to trace processor instruction execution step-by-step, and examine the contents of debug logs gives us the abilities we need to observe, access, and control system operation during development. 

SiFive Insight is the first RISC-V core with pre-integrated debug and trace offering. SiFive Insight reduces complexity by offering a single-vendor solution that is lightweight and simple to integrate into SoC designs based on SiFive RISC-V processor Core IP. Uniquely, SiFive Insight supports Arm® Coresight™ to enable simple adoption and ease of use in a heterogenous SoC development environment. 

SiFive Insight is pre-integrated and verified in a single deliverable, to offer a range of debug and trace functions as standard. From run-control to advanced multi-core trace in a heterogeneous core complex, SiFive Insight can be easily configured using the [award-winning](https://www.elektraawards.co.uk/elektraawards2019/en/page/2019-winners) SiFive Core Designer to suit your needs. 

![SiFive Insight Core Designer Integration](https://images.prismic.io/sifive/0894b85b-23f3-4d9e-8ac8-752627e2e3d5_sifive-core-designer-insight.png?auto=compress,format)

All SiFive cores include the ability to be configured with up to 16 hardware triggers. Hardware triggers can stop the processor on the execution of an instruction or the read or write of a memory location. Furthermore, hardware triggers can be used to control trace collection. These triggers can be combined to support arbitrary ranges. In addition to core triggers, SiFive Insight supports a configurable number of external triggers allowing for external events to trigger a debug halt. 

SiFive Insight is compatible with [Nexus 5001™ trace](https://nexus5001.org/nexus-5001-forum-standard/) specification standards, and is fully supported by the SiFive Freedom Studio integrated developer environment (IDE). Compatibility with Nexus 5001™ trace also ensures compatibility with leading developer tools. SiFive cores support the recently ratified [RISC-V Processor Trace standard](https://riscv.org/2020/03/risc-v-foundation-announces-ratification-of-the-processor-trace-specification/). The RISC-V Foundation trace and debug working group is evaluating Nexus 5001™ trace as an additional standard to be ratified. SiFive works closely with our ecosystem partners to enable them with the latest SiFive Insight technology, ensuring that they are well-positioned to support application developers and chip designers. 

*[IAR Systems](https://www.iar.com/products/architectures/risc-v/)* 
![](https://images.prismic.io/sifive/7b100e2c-c4f1-4a71-924c-d28f055cafe4_iar_probe%26adapter_kit_2.jpg?auto=compress,format)
*[Lauterbach](https://www.lauterbach.com/frames.html?home.html)* 
![](https://images.prismic.io/sifive/8f898c81-4aee-443d-a5f0-9411fc238c1d_RISC-V_Nexus_trace_Lauterbach.png?auto=compress,format)
*[SEGGER](https://segger.com)* 
"SEGGER J-Link offers full support for the new SiFive Insight debug and trace IP, including the Nexus based trace implementation. With SEGGER J-Link the trace data can be read from on-chip memory, yielding back trace, execution counts, code profiling and code coverage information" - SEGGER Microcontroller GmbH
![](https://images.prismic.io/sifive/18ebdd7e-6fdd-417a-b9d7-f7ec8b630e2f_SEGGER-Jlink-Ozone-Debugger.png?auto=compress,format)

**Market Momentum** 
Industry analysts forecast [62.4 billion RISC-V cores](https://riscv.org/2019/11/9679/) will be deployed in the next 5 years. SiFive’s portfolio of products, tools, and expertise will ensure the development of your new market-focused product is secure, efficient, and free of bugs.

sifive-insight-bullets.png

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad.
 
The first day of the event was the symposium portion, and it was attended by students of various universities, research scholars, and many prominent industrial experts from Ahmedabad. Anand Bariya, VP of engineering at SiFive, delivered a keynote presentation that outlined the importance of the RISC-V ISA and SiFive’s role in advancing the open-source ecosystem. Another keynote was presented by Professor Usha Mehta of Nirma University, Ahmedabad, who spoke on the research activities currently taking place at the university. Rajesh Varadharajan, the director of IP engineering at SiFive, presented on RISC-V core IP for target vertical markets and software ecosystems, and also provided a tutorial on SiFive’s Core Designer. Approximately 160 people participated in the symposium.

The second day of this two-day event was a hands-on workshop where attendees were given the opportunity to practice what they learned on the previous day. All the participants were very enthusiastic to implement the RISC-V ISA and boot their program on an FPGA board. Approximately 130 people participated in the workshop, as the seats were limited.
The experience in Ahmedabad was very rewarding. The enthusiasm of the participants from various backgrounds made it a great success! We’re very thankful to the management and staff of Nirma University for their gracious support and for co-hosting the event!

For more information on these and our many other tech symposiums and workshops, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com).
 
## Glimpses: Day-1:
![Glimpses Day 1](https://images.prismic.io/sifive/d7343270-2b16-498f-a1cd-9a643192e516_glimpses-day-1.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/e82e6e85-2c01-4ffa-a430-70a79ae3c546_glimpses-day-1a.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/18a138f5-ebef-4aec-a9ac-2fbb093171eb_glimpses-day-1c.png?auto=compress,format)
![Glimpses Day 1](https://images.prismic.io/sifive/74733ec9-eaf7-434e-81e8-dfe4d6bfbee3_glimpses-day-1b.png?auto=compress,format) 

## Glimpses: Day-2:
![Glimpses Day 2](https://images.prismic.io/sifive/7208f507-9d99-453c-bf71-5708b614c4e2_glimpses-day-2.png?auto=compress,format)
![Glimpses Day 2](https://images.prismic.io/sifive/0339e334-23a0-4dd3-a282-7c19579bca77_glimpses-day-2b.png?auto=compress,format)
![Glimpses Day 2](https://images.prismic.io/sifive/c588b393-86ca-471d-8ef5-72db71a1db7c_glimpses-day-2c.png?auto=compress,format)

The RISC-V Revolution is Going Strong in Ahmedabad

Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the continued networking and idea sharing that open source brings to the hardware community.

Western Digital co-hosted the symposium in Costa Rica, which was co-located with LASCAS 2020, the flagship conference of the IEEE Circuits and Systems Society in Latin America. Those who attended the presentations and participated in the hands-on workshop included folks from Intel, HP and Wind River, as well as graduate students and professors from Central and Latin American countries. One of the highlights was the keynote presentation by Gerardo Bertero, senior director at Western Digital, who spoke about memory architecture and how RISC-V is being used within Western Digital.

With the Computer Research Center at National Polytechnic University (CIC-IPN) as our co-host, the symposium in Mexico City drew over 70 attendees. This symposium was predominantly geared toward academia and was heavily attended by students and professors from a variety of disciplines. One of the highlights was the presentation by Professor Marco Ramirez Salinas who outlined the magnitude of RISC-V research taking place at the university. It was very impressive to hear about the university’s accomplishments with RISC-V. 

We’d like to offer our gratitude to both Western Digital and CIC-IPN for co-hosting these symposiums with us.

For more information on these and our many other tech symposiums and workshops, please visit [sifivetechsymposium.com](https://sifivetechsymposium.com/) 

## Snapshots 
![Costa Rica John Min-Feb-25-2020](https://images.prismic.io/sifive/7fa5064a-28c1-4fa9-a89c-427c11592cc4_costa-rica-john-min-feb-25-20.jpg?auto=compress,format)
![Costa Rica David Connelly-Feb-25-2020](https://images.prismic.io/sifive/e78996ae-0c42-4e8f-8399-672fe6575d78_costa-rica-david-connelly-feb-25-20.jpg?auto=compress,format)
![Mexico Workshop-2020](https://images.prismic.io/sifive/7beada70-ba68-40e8-b4d7-a52a885e9625_mexico-workshop-2020.jpg?auto=compress,format)
![Mexico Workshop-2020 v2](https://images.prismic.io/sifive/1e419d40-1790-4fb7-81b5-102d1530f379_mexico-workshop-2020-v2.jpg?auto=compress,format)
![Mexico Workshop-2020 v3](https://images.prismic.io/sifive/1349bab7-3fc6-4f54-a118-47aef6543c98_mexico-workshop-2020-v3.jpg?auto=compress,format)

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia



This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memory, and data transfers between DSA and memories. This fourth instalment in the series will focus on the frequent interaction with and amongst cores, which is required by DSAs, and how the TileLink specification can be utilized to build interconnection networks. 

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements.  Examples of DSAs include compression/decompression units, random number generators and network packet processors.  A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1). 

![AXI Bus](https://images.prismic.io/sifive/22db71b5-55c6-45cf-8365-9b7ae7855e36_axi-bus-figure1-2.jpg?auto=compress,format)

SOCs based on RISC-V offer a unique opportunity to optimize data transfers between cores and DSAs.  Many high-performance DSAs require frequent interaction with and amongst cores.  Standard memory interconnects often are limited by how fast they can transfer data.  Such an interconnection can be designed to the TileLink specification [1], which is a free and open standard to build interconnection networks. 
  
Designing one’s own memory interconnection network offers several advantages to a DSA (Figure 2): 
- The DSA can connect to the memory interconnect to reduce latency of interaction with cores by directly participating in the memory coherence protocol. 
- The interconnect channel width can be optimized to the data transfer rates required by the DSA.  For example, one could envision extremely wide 1024-bit wide channels.  The interconnection channels can also be run at a higher frequency than what a standard interconnect might allow.
- The Last-Level Cache (LLC) can have bigger cache block sizes than the core caches.  For example, core caches typically have 64-byte blocks, whereas the LLC could be designed for 128-byte or 256-byte cache blocks. The LLC can also support special prefetch mechanisms optimized for the DSA. 
- The LLC and interconnect can offer different levels of QoS (Quality of Service).  These QoS levels can be used, for example, by the LLC controller, to offer lower latency and higher bandwidth to DSAs in the presence of cross-traffic from different applications.

[1] SiFive TileLink Specification, [tilelink spec 1.8.1 PDF](https://sifive.cdn.prismic.io/sifive/7bef6f5c-ed3a-4712-866a-1a2e0c6b7b13_tilelink_spec_1.8.1.pdf)

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)




Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V



This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance. Part #2 addressed the challenges associated with point-to-point ordering between cores and DSA memory, and how RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores and DSAs. This third installment will focus on the challenges associated with data transfers between DSA and memories, such as DDR, LPDDR or HBM, and explain how SoCs based on RISC-V can use an alternate approach to write the data directly to memory.

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements.  Examples of DSAs include compression/decompression units, random number generators and network packet processors.  A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1).

![High Banswidth Accelerator](https://images.prismic.io/sifive/83e22f95-0216-42ac-951e-145f1ec99cc1_high-bandwidth-accelerator.jpg?auto=compress,format)

SoCs based on RISC-V offer a unique opportunity to optimize high-bandwidth data transfers between a DSA and memory.  DSAs often need to transfer their data to memory, such as DDR, LPDDR or HBM memories.  Often this is accomplished using a DMA (Direct Memory Access) engine.  
 
The difficulty in the traditional approach (Figure 1) is that such data transfers often involve allocating the data in the Last-Level Cache first.  This can significantly slow down accesses, particularly if the volume of transferred data is greater than the size of the Last-Level Cache. 

Figure 2 shows that SoCs based on RISC-V can use an alternate approach where they can write the data directly to memory, bypassing the Last-Level Cache.  This can be achieved by marking the data being written as uncached. Alternatively, the DMA engine can provide a hint to the Last-Level Cache to not allocate the data in the Last-Level Cache, but to write directly to memory.  In this scenario, the data is still marked as cacheable, so any other cached copy of the data must be invalidated within the processor complex. 

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)



Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

*A Note from Chris Lattner, New SVP of Platform Engineering* 

My quest is to build beautiful things that help change the world, and I’ve been fortunate to spend the last 15 years in Silicon Valley, working with some of the major players shaping all sorts of technology. Today, I’m super excited to join SiFive - the company I believe is best positioned to transform the silicon industry, to lead the Platform Engineering team. With [experience](http://nondot.org/sabre/Resume.html) building and leading large-scale production systems that power our industry, I’m looking forward to making the dream of customized chips a reality with SiFive’s amazing team of engineers. 

The end of Moore’s Law is a profound time, leading to new accelerators, new demand for custom ASICs, and new opportunities - and I believe that it is time for the semiconductor industry to change its approach to innovation. This industry has been defined by proprietary technologies that are difficult to use, don’t inter-operate well, and have poor user experience. I believe that open tooling, world-class engineering, and a focus on end-to-end user experience can transform the industry. Similarly, the RISC-V architecture provides unique opportunities for SoC customization at every level. This is only possible with SiFive’s ambitious design methodology, which is unmatched in the industry. 

My background includes experience creating and leading a number of large-scale technologies, including compiler technologies like the LLVM Compiler Infrastructure project, the Clang C and C++ compiler, the MLIR machine learning infrastructure, and others. I also spearheaded the creation of Swift - a programming language that powers Apple’s ecosystem - and led a team at Tesla that applies a wide range of tech in the autonomous driving space. Most recently, I built and managed an array of AI-related compiler, runtime, and programming language teams for Google Brain and TensorFlow. 

I’m extremely thankful for the opportunities I’ve had in my career, but I’m even more excited to join the ambitious and world class team at SiFive, who are tackling an even bigger project: making custom silicon more accessible through SiFive’s design platform. SiFive's vertically integrated, idea-to-silicon team is an incredible one-stop-shop, making it possible to develop end-market hardware faster and more affordably than ever before. 

Faster, better, and cheaper custom SoC development will make it more accessible, and will allow people everywhere to accomplish technological breakthroughs that couldn’t happen anywhere else. Let’s change the world together! 

 - Chris

ChrisLattner-Blog.PNG



This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-grain communication between them and improve core-DSA interaction performance.

To recap, a DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus (Figure 1).

![AXI Bus](https://images.prismic.io/sifive/07e6b833-dfff-4803-a824-354b0d2405cc_axi-bus.jpg?auto=compress,format)

RISC-V offers a unique opportunity to optimize high-bandwidth communication between cores and DSAs. Cores often issue fine-grain load and store instructions in the IO space to access DSA memory. The problem, however, is that these loads and stores to DSA memory might have side effects. For example, a load to a specific DSA memory address might trigger a network message as a side effect of the load. Typically, because of such side effects, loads and stores from a core to an IO device are required to be observed by the IO device in order. This is also known as point-to-point ordering.

A naive way to implement such point-to-point ordering is to issue a load to a DSA and wait for the result to return to the core (Figure 2). This is highly inefficient because successive loads or stores to DSA memory cannot be issued back-to-back in a pipelined fashion. A RISC-V implementation would typically implement such IO loads in a pipelined fashion with help from the interconnect between the core and DSA (Figure 3). For example, if a mesh topology uses a fixed path (e.g., X-Y routing) from the core to the DSA (perhaps via the IO bridge), then the interconnect can guarantee the ordering and thereby allow very high bandwidth access to DSA memory

The RISC-V architecture itself offers two other modes of optional IO ordering. First, RISC-V offers a very conservative IO ordering mode, which can be selectively used to guarantee strong ordering when necessary. Second, RISC-V offers a high-bandwidth relaxed ordering mode where IO loads and stores can be reordered. This mode would typically be used for DSA memory that does not have side effects.

See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)




Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V



This is the first in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus. 

![IO Caching Slide](https://images.prismic.io/sifive/794e06be-0553-4c49-bc09-cc2736113b1d_IOCachingSlide.jpg?auto=compress,format)

Unfortunately, data transfers between DSAs and the core complex, which are often critical, can be inefficient in traditional SoCs.  Figure 1 shows that the datapath between a DSA and core complex in a traditional SoC traverses multiple interconnects 
and bridges.  This increases the latency between the cores and a DSA to 100s of cycles. Consequently, this makes it difficult to have fine-grain interaction between cores and a DSA.
 
RISC-V offers a unique opportunity to optimize such fine-grain communication between cores and DSAs. For example, as Figure 2 shows, a DSA can export a per-core DSA cache sitting next to a RISC-V core. The RISC-V core can poll status changes out of the DSA cache, thereby reducing the latency of interaction between the core and DSA to tens of cycles. The DSA can update 
status changes in the DSA cache through a sideband network. Others [1, 2] have argued for similar mechanisms.  
 
The DSA cache can further improve core-DSA interaction performance by prefetching data from the DSA and merging small IO writes into bigger chunks. A RISC-V core could even integrate some of these mechanisms within the core pipeline, if one were to design a custom RISC-V core.

[1] J. Mcalpin, "Notes on Cached Access to Memory-Mapped IO Regions", 
[https://sites.utexas.edu/jdm4372/2013/05/29/notes-on-cached-access-to-memory-mapped-io-regions](https://sites.utexas.edu/jdm4372/2013/05/29/notes-on-cached-access-to-memory-mapped-io-regions/)
 
[2] Mukherjee, et al., "Coherent Network Interfaces for Fine-Grain Communication," Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996.
 
See more details about SiFive’s standard cores, or to customize and build domain-specific RISC-V cores, please visit [sifive.com/risc-v-core-ip](https://www.sifive.com/risc-v-core-ip)



Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V

The RISC-V ISA is rapidly becoming the new standard for compute, and has literally spawned a worldwide revolution in the semiconductor industry. At the beginning of 2019, SiFive set out to foster education about SiFive’s RISC-V based technologies and to advance deeper collaboration within the global hardware community. We succeeded! We completed 52 Tech Symposiums/Workshops reaching 26 countries and six continents – reaching all corners of the world. Over 10,000 people attended these events, demonstrating strong attraction to RISC-V in not only industry, but in academia as well.

![SiFive Tech Symposium](https://images.prismic.io/sifive/11502522-4461-4109-af6b-ba58e657f47f_sifive-tech-symposium-world-map.jpg?auto=compress,format)
![SiFive Tech Symposium Event Dates](https://images.prismic.io/sifive/8c325b66-f8de-4a39-a9de-336f6debc7e0_symposium-event-dates.jpg?auto=compress,format)

We’d like to express our gratitude to our co-hosts around the world who made all of this possible. 

![Partner Logos](https://images.prismic.io/sifive/7a301b3c-ac7e-46ac-af0e-c2d895d4183a_partner-logos.jpg?auto=compress,format)

We’d also like to thank all of our partners around the world who sponsored and/or promoted the symposiums and workshops.
![Sponsors Logos](https://images.prismic.io/sifive/ed338905-6191-4d7e-a003-d331b327aca3_sponsors.png?auto=compress,format)

Last, but certainly not least, we’d like to thank all of the invited speakers who shared their knowledge, expertise and enthusiasm about RISC-V. Over 150 speakers presented!

This tour has allowed us the opportunity to meet so many new people, who are now our friends. A lot of great memories were made.

We wish you happy holidays. We are looking forward to working with each and every one of you in 2020.

SiFive Completes its Global 52-City Tech Symposium/Workshop Tour



We completed our tour through South America, which included tech symposiums and workshops in São Paulo, Porto Alegre, Montevideo, Buenos Aires and Bucaramanga. We are proud to have co-hosted these events with South America’s most prestigious universities, including the Polytechnic School of the University of São Paulo (Poli-USP), the Federal University of Rio Grande do Sul (UFRGS), the Universidad Católica del Uruguay (UCU), the University of Bueno Aires (UBA), the Universidad Industrial de Santander (UIS), and the Integrated Systems Research Group Onchip at UIS. The combined attendance was 300+, which demonstrates the strong interest that South Americans have in RISC-V.

São Paulo, Brazil Symposium and Workshop (11/18):
![São Paulo, Brazil Symposium and Workshop (11/18)](https://images.prismic.io/sifive/b2cb58a8-b909-4077-ad88-1a55c578dabf_Sao-Paulo.jpg?auto=compress,format)

Porto Alegre, Brazil Symposium and Workshop (11/19):
![Porto Alegre, Brazil Symposium and Workshop (11/19)](https://images.prismic.io/sifive/ed902781-b426-4ebf-922c-e486ec0cc1ce_Porto-Alegre.jpg?auto=compress,format)

Montevideo, Uruguay Symposium and Workshop (11/21):
![Montevideo, Uruguay Symposium and Workshop (11/21)](https://images.prismic.io/sifive/3fc7b88e-da46-4b88-8358-5e566a41b79e_Montevideo.jpg?auto=compress,format)

Buenos Aires, Argentina Symposium and Workshop (11/22):
![Buenos Aires, Argentina Symposium and Workshop (11/22)](https://images.prismic.io/sifive/06db14c4-0873-41e5-9560-4134611c679c_Buenos-Aires.jpg?auto=compress,format)

Bucaramanga, Colombia Symposium and Workshop (11/25):
![Bucaramanga, Colombia Symposium and Workshop (11/25)](https://images.prismic.io/sifive/fb27f1c6-29e6-4e03-b394-3a6323200e22_Bucaramanga.jpg?auto=compress,format)

At all five symposiums, the main highlight was the hands-on workshop that offered attendees the unique opportunity to configure their own RISC-V core and bring up on an FPGA. Working professionals and students were enthusiastic about what they learned in the workshop and expressed their desire to continue using the RISC-V ISA for their current and future projects. We were humbled by the warm welcome we received by both academia and the local and regional electronics industry. In addition to our co-hosts, we’d like to express our gratitude to our South American partners, including Centro Interdisciplinar em Tecnologias Interativas (CITI-USP), the Department of Electronic Systems Engineering at the Polytechnic School of the University of São Paulo (PSI-EPUSP), the IEEE Uruguay Section and the IEEE Colombia Section. 

The RISC-V Revolution has reached South America!


SiFive’s Tech Symposiums and Workshops Throughout South America Included Participation by Both Academia and Industry



SiFive’s Tech Symposiums in Pakistan were a huge success, with the participation of more than 2,500 people from across the country. One of the symposiums was held at the NED University of Engineering and Technology in Karachi, and the other took place at the University of Engineering and Technology in Lahore. We are grateful to both of these universities for co-hosting these events with us, and to Lampro Mellon for partnering with us. All three were instrumental in making these symposiums world-class events. Attendees included students and professors, as well as delegations from federal and state governments of the Islamic Republic of Pakistan. The policy-making officials from the IT and education ministry also participated very actively in the symposiums. Everyone was extremely motivated and enthusiastic to learn more about the RISC-V ISA and the latest innovations. There were informative and engaging presentations by Naveed Sherwani (President & CEO), Krste Asanovic (Co-Founder & Chief Architect), Yunsup Lee (Co-Founder & CTO), Thomas Xu (CEO, SiFive China), Shafy Eltoukhy (SVP, Silicon BU), Anand Bariya (VP, Engineering), Muhammad Ahmed (Architect) and many others.

The symposium witnessed the first and formal adoption of RISC-V as the architecture of choice for all public universities in Pakistan’s Punjab Province. An MOU was signed in the presence of HE Sardar Usman Buzdar (Chief Minister of Punjab), Mr. Raja Humayun (Minister of Higher Education, Punjab Province), Krste Asanovic (SiFive), Naveed Sherwani (SiFive), Sabahat Rafiq (CEO, Lampro Mellon), Thomas Xu (SiFive China), Dr. Shafy Elthouky (SiFive), Chairman of Punjab Planning Division, Chairman of Punjab Higher Education Commission, Vice Chancellor of UET Lahore, Mr. Farooq Arshad (PTI Information Secretary), among other distinguished guests in Lahore.
## Glimpses of the Event:
![SiFive Tech Symposiums in Pakistan](https://prismic-io.s3.amazonaws.com/sifive/9e4cfaf3-71c6-4c31-b1c0-353b8e5ec799_pakistan-event.jpg)
![Yunsup Lee](https://prismic-io.s3.amazonaws.com/sifive/3d2b151a-6b6f-4a4c-a7ec-c8275dd87f69_yunsup-lee.jpg)
![Over 3,500 in attendance](https://prismic-io.s3.amazonaws.com/sifive/cb353cd3-9c6e-4313-9e25-0f83255df6f3_event-3-500.jpg)
![SiFive’s Tech Symposiums](https://prismic-io.s3.amazonaws.com/sifive/8d32a2f6-9878-47dc-9210-1b893bd0eb0a_symposiums-in-pakistan.jpg)

For more information on these and our many other tech symposiums and workshops taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)




Our SiFive Tech Symposiums in Pakistan Drew Over 2,500 Attendees!



Our tour through the Middle East region included Istanbul, Amman, Cairo, Abu Dhabi and Dubai. This tour was dedicated to academia, and included presentations, tutorials and hands-on workshops. Attendees primarily consisted of PhD research scholars, professors and engineering students. It was humbling to see that the region’s universities have included the book, The RISC-V Reader: An Open Architecture Atlas, authored by SiFive Technical Adviser David Peterson and Co-Founder and Chief Engineer Andrew Waterman, in their curriculum. Besides presentations and tutorials, the attendees showed keen interest in the workshop. One could see the sense of achievement among the students on their successful completion of the workshop. It opened their minds to the infinite possibilities for exploring their unique ideas and realizing them into working products. The universities also showed desire to collaborate with SiFive on RISC-V research and development. Through these symposiums and workshops, SiFive has left its footprints in the Middle East region.

We would like to express our gratitude to our co-hosts – Mentor, TÜBİTAK BİLGEM, The University of Jordan, IEEE Jordan Section, EiTESAL, The American University in Cairo, the Artificial Intelligence and Intelligent Systems Institute (AIISI), Khalifa University, and BITS Pilani Dubai Campus. We’d also like to thank eFabless for their partnership.

For more information on these and our many other tech symposiums and workshops taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)

![Istanbul,Turkey](https://prismic-io.s3.amazonaws.com/sifive/4a4bdd9f-4728-4dbd-b8de-fe35c71b8610_istanbul-symposium.png)
![Amman Workshop](https://prismic-io.s3.amazonaws.com/sifive/97257bd8-932c-4acb-ad90-c9f7c520875d_amman-workshop.png)
![Amman Workshop](https://prismic-io.s3.amazonaws.com/sifive/80639bb1-cc28-403e-ae15-d058d0de1ff4_amman-workshop-2.png)
![Cairo,Egypt](https://prismic-io.s3.amazonaws.com/sifive/f36fb4a3-e63e-43cc-8ec2-3a73bb5c6b9b_cairo-symposium.png)
![Cairo Workshop](https://prismic-io.s3.amazonaws.com/sifive/efd0cb98-f0a8-41ff-9244-6d7c95e4d411_cairo-workshop.png)
![Abu Dhabi](https://prismic-io.s3.amazonaws.com/sifive/c0aa7d94-87a5-46dd-a373-63fcc2a6f2a2_abu-dhabi.png)
![Dubai, UAE](https://prismic-io.s3.amazonaws.com/sifive/5c6d2cc0-0450-421c-9224-eda344869b67_dubai-workshop.png)

We Just Completed Five Energy-Filled Tech Symposiums and RISC-V Workshops Throughout the Middle East Region



Our SiFive Tech Symposiums in Portland and Seattle were a big success, thanks in large part to our co-host, Mentor, a Siemens business; and our partner, Lauterbach, a leader in microprocessor development tools. Many leading OEMs were in attendance, such as Amazon, Facebook, Intel, Microsoft and Google  There were presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners. We’d like to offer our thanks to the faculty and students at Portland State University for their participation at the symposium in Portland. We’d also like to thank the RISC-V Seattle Meetup Group who actively participated at the symposium in Seattle.

We’re now headed to South America for our next exciting round of symposiums and workshops. For more information on these and our many other tech symposiums taking place around the globe, please visit [www.sifivetechsymposium.com](https://www.sifivetechsymposium.com)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/4531c1dc-7165-4ce8-bb8f-bd0416cb9a5c_SiFive-tech-symposiums-portland-1.jpg)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/98b9705e-c532-4ea7-b2db-0a850bb75d65_SiFive-tech-symposiums-portland-2.jpg)

![The SiFive Tech Symposiums in Portland](https://prismic-io.s3.amazonaws.com/sifive/245e1370-8d0d-4e86-8f15-58ca73ead363_SiFive-tech-symposiums-portland-3.jpg)

![The SiFive Tech Symposiums in Seattle](https://prismic-io.s3.amazonaws.com/sifive/a908b542-2392-447f-ab1c-5308e93362c8_SiFive-tech-symposiums-seattle-1.jpg)

![The SiFive Tech Symposiums in Seattle](https://prismic-io.s3.amazonaws.com/sifive/ce4ccbf1-1993-4c31-8a9e-6390e356397b_SiFive-tech-symposiums-seattle-2.jpg)

The SiFive Tech Symposiums in Portland and Seattle are a Wrap

**Introducing the new SiFive U8-Series Core IP**

![SiFive U8-Series](https://prismic-io.s3.amazonaws.com/sifive%2F5880fe27-e76b-4136-a379-273141edda84_sifiveu8seriesresize.png)

SiFive is pleased to introduce the SiFive U8-Series Core IP, an incredibly scalable high-performance microarchitecture for modern SoC designs.  The SiFive U8-Series is the highest performance RISC-V ISA based Core IP available today, based on a superscalar out-of-order pipeline with configurable pipeline depth and issue queue width. SiFive U8-Series Core IP is designed for use in performance- and latency-sensitive markets, such as automotive, datacenter attach, and edge or end point deep learning SoCs.

The needs of the modern world to solve problems using deep learning and real-time low latency processing are increasing compute workloads in the enterprise, and migrating tasks into the edge and end point. Domain specific SoCs are being used to localize compute to reduce latency, improve workload performance, and increase efficiency. The requirements of modern SoCs include scalable processor cores that span current process technology, enabling configurable designs, and permit customization.

![SiFive U-Series Cores](https://prismic-io.s3.amazonaws.com/sifive%2Fcf9d84fb-392f-4bb7-ad11-00f4670be4df_fig1-u-core-series.png)

Based on the open, freely available RISC-V ISA, SiFive U8-Series Core IP is well-positioned to address these challenges. The SiFive 8-Series microarchitecture is fully parameterized to enable the generation of a vast array of configurations, allowing customers to explore the design space and fine-tune performance and features to the desired workload. 

**SiFive U8-Series Standard Cores**

SiFive will initially offer two standard cores in the SiFive U8-Series Core IP lineup. The standard core offerings will be the SiFive U84 core, optimized for power efficiency and area efficiency, and the SiFive U87 core with vector processing. The SiFive U84 design, focused on optimized efficiency, is the lead standard core, with more details on the SiFive U87 design to be released later.

![SiFive U84 & U87 Standard Core IP](https://prismic-io.s3.amazonaws.com/sifive%2F2477c5bd-c103-4a3d-b4de-e2ee24c74999_fig2-u84u87.png)

**Incredible, Efficient Performance**

Generationally, the SiFive U84 core offers a startling 3.1X higher performance than SiFive's popular U74 standard core. This is enabled by a 2.3X increase in IPC combined with a 1.4X increase in maximum frequency capability. Shown below, the SiFive U84 is 5.3X higher performance than the SiFive U54, isolated process. The SiFive U84 standard core in 7nm is 7.2X higher performance compared to a SiFive U54 standard core in 28nm. 

![SiFive U-Series Generational Performance](https://prismic-io.s3.amazonaws.com/sifive%2Fe015d8b5-a552-4f04-a2a0-da1e26c8375d_fig3-relativeperfu84.png)

**Winning Area Efficiency**

A quad-core SiFive U84 CPU, including 2MB of L2 cache, requires only 2.63mm2 in 7nm process technology while capable of operating at up to 2.6GHz clock speed. A single SiFive U8-Series CPU core, without L2 cache, can be laid out in as little as 0.28mm2. This massive area reduction without performance impact reduces overall solution cost, or allows the use of silicon area for new compute functions. 

![SiFive U84 Highlights](https://prismic-io.s3.amazonaws.com/sifive%2Ff24327ab-e4e6-429a-a0b9-9215824047ab_fig4-u84ppa.png)

The SiFive U84 standard core offers an incredible increase of 2X better area efficiency1 and 1.5X better performance/watt1, with very competitive performance when compared to an Arm® Cortex®-A72 processor. 

**Class-Leading Scalability**

SiFive U8-Series Core IP will be available on a variety of process nodes, from mass-market to leading-edge. The availability of verified IP with modern high-performance CPU features across such a broad array of foundry options defines the SiFive U8-Series as leading the market in scalability for design target and SoC design support. 

SiFive U8-Series scalability doesn’t end there, with the ability for SiFive customers to configure options inside the entire Out-Of-Order design space hyperplane. While the SiFive U84 standard core is configured with a 12-stage pipeline and triple-issue capability, the pipeline depth, issue queue count, and other options can be adjusted to perfectly suit the target market applications. 

SiFive U8-Series microarchitecture scalability options include the capability to cross-issue from the integer unit to the floating point unit, when the FP queue is empty. This flexibility when combined with design scalability of number of issue queues, and FP units in the design, can offer significant performance increases depending on the workload. 

SiFive U8-Series Core IP also features composable caches, enabling real-time operation support. For markets where low-latency, deterministic behavior is required, the ability to configure the high-performance OoO core to operate deterministically while maintaining the advantages of tiny area and superb efficiency makes SiFive U8-Series the obvious choice for automotive, enterprise, and edge or end point AI markets. 

**SiFive Mix+Match**

SiFive offers the ability to support heterogeneous core complexes, composed of different class cores. SiFive Mix+Match enables the design of core complexes with a mix of cores to enable the right level of processing capabilities for the target workload. On top of this, SiFive Custom Instruction Extensions permit any core to be enabled with new instructions to make workload acceleration simple and easy. Custom Accelerator IP from 3rd parties can be coherently included with SiFive’s TileLink coherent fabric for core-to-core communication, or SiFive ChipLink coherent fabric for chip-to-chip communications. 

![SiFive Mix+Match Example](https://prismic-io.s3.amazonaws.com/sifive%2Ff556a53c-f0d3-4886-b079-6077d80cf3ad_fig5-mix%2Bmatch.png)

SiFive also offers high-bandwidth memory interface IP, supporting SiFive TileLink and industry standard protocols, for SoC or chiplet style designs for memory intensive workloads that require the latest HBM2E+ memory capabilities. With validation in 7nm and 12nm process technology currently in progress, SiFive is extending high-performance DRAM capabilities from existing 16nm processes to leading-edge technologies. 

**Summary**

Today’s introduction of the new, high-performance SiFive U8-Series Core IP begins a new chapter for modern SoC design. Performance, area efficiency, and energy efficiency are key metrics for chip designers, and the SiFive U8-Series is compelling on all fronts. SiFive’s unique configurable methodology for fine-tuning IP to customer requirements unlocks the full potential of next-generation SoCs for markets that require high-performance application processor cores. 

SiFive now welcomes lead access to the new, high-performance SiFive U8-Series of application processor Core IP - please contact SiFive to find out more on how your next modern SoC design can benefit. 

**Footnote**

1 – Based on SiFive internal estimates of SPEC Int/GHz per Watt, and Power per MM2 of SiFive U84 Core with L2$ vs Arm® Cortex®-A72, of core implementation in 16nm process technology.
2 – Based on SiFive internal estimates compared to SiFive U7-Series using iso-process & iso-frequency methodology.

©2019 SiFive, Inc. All rights reserved. All trademarks referenced herein belong to their respective companies. PCI-SIG®, PCIE® and the PCI HOT PLUG design mark are registered trademarks and/or service marks of PCI-SIG. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 

sifiveu8seriesresize.png

Incredibly Scalable High-Performance RISC-V Core IP

## Securing The RISC-V Revolution


![SiFive Shield](https://prismic-io.s3.amazonaws.com/sifive%2F0ebdcb30-26a9-4298-943d-8e31149556ba_sifiveshieldresize.png)

SiFive Shield is an open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The needs of modern SoC design dictate the need for a scalable solution for security, offering a low trusted computing base with clear root-of-trust and crucially, is auditable. Customization is also key, as a single offering fits all approach does not align to the needs of the next generation of domain specific processors now being designed.


Securing the RISC-V revolution requires a scalable architecture that offers per-memory protected memory regions and multi-core privilege modes. SiFive Shield and SiFive WorldGuard enable a scalable architecture with the ability to offer greater isolation. 

## SiFive WorldGuard

![SiFive WorldGuard](https://prismic-io.s3.amazonaws.com/sifive%2F7867de53-549f-4b13-995f-bdeceead7bcd_sifiveworldguard.png)

SiFive WorldGuard is a fine-grain security model for isolated code execution and data protection. SiFive Worldguard offers SoC level information control with advanced isolation control, based on multiple levels of privilege per world, and an unlimited amount of worlds. SiFive WorldGuard offers core-driven and process-id driven modes for multi-domain security, to offer data protection for core, cache, interconnect, peripheral, and memory. 

![Figure 1 - Core Driven Mode](https://prismic-io.s3.amazonaws.com/sifive%2F43aedfe6-dd30-4e11-aefc-a63e53f83558_fig1-worldguardcoremode.png)

In a multi-core processor, shown above, World ID markers are used to isolate processes from each other to ensure protected and isolated execution. Inside the SoC, the WID marker extends from core to cache, interconnect, peripherals, bus masters, DMA regions, and memories. Applications or OS environments can be isolated and protected, inside a high-performance multi-core system. For embedded systems where a single core is more common, the use of PID driven world ID's to protect and isolated execution between user and machine mode, for example. 

![Figure 2 - PID Driven Mode](https://prismic-io.s3.amazonaws.com/sifive%2F485845b3-6b68-41e7-9af1-b782ee722f05_fig2-worldguardprocessmode.png)

SiFive WorldGuard hardware accelerated multi-domain security moves the industry well beyond a single zone of trust. 

## Root of Trust

A clear root of trust is critical for enabling security. SiFive Shield offers secure on device storage of keys, with per device unique IDs. This enables flexible key management to support key and certificate provisioning at time of manufacture, critical to the beginning of secure lifecycle management. SiFive’s root of trust is based on open specifications and an open-source software platform for clear audibility.  

## Threat Prevention

Secure SoC design is enabled by accurate threat modelling. Inside of an SoC, the flow of information for processing requires an array of technologies. Fault detectors for the SoC ensure that operation continued as intended, to deter physical tamper attacks. Physical Memory Protection (PMP) and Physical Memory Attributes (PMA) are supported in 
the RISC-V ISA and leveraged by SiFive Shield to set limitations on memory ranges and memory mapped peripherals by privilege, enabling scalable domain security. 

Build upon the open and freely available RISC-V ISA enables a new approach to security. Building an open, secure platform architecture for security that can scale is the main goal of SiFive Shield.

## Verified Crypto-Engines

The SiFive Shield architecture includes a NIST SP 800-90A/B/C compliant true random number generator (TRNG) to enable cryptographic or entropy based secure features. The Cryptographic engines are protected against SPA/DPA/EMA attacks, and enable support for common use cases. The AES cryptographic engine offers block cipher and authenticated encryption support, while the secure hash crypto-engine support SHA-2 and SHA-3 standards. Public Key cryptographic RSA and ECDSA support is also offered. The cryptographic library is subject to external lab verification to ensure correct operation and validity. 

## Software

SiFive offers a single software platform based on open-source software. Figure n indicates the mix of community open-source software, including FreeRTOS and Linux OS support for SiFive RISC-V based SoCs. Further development is enabled via the SiFive Freedom Metal and Freedom SDK tool chains that offer a full development environment. 

## Summary

SiFive Shield is a new, transformative technology for securing RISC-V based SoCs. With an open, top-down security platform specification designed to provide a clear root of trust, low trusted codebase, effective lifecycle management, and a class-leading SiFive WorldGuard security model, the RISC-V revolution is secured by SiFive Shield. 

![Figure 3 - Competitive Comparison](https://prismic-io.s3.amazonaws.com/sifive%2Fa3fd17c8-840a-4d61-9be6-098d03e3b9e3_fig3-sifiveshieldcomparison.png)

SiFive_Shield_Metal_WordMark.png

SiFive Shield: An Open, Scalable Platform Architecture for Security



We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. 

The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have been significantly instrumental in engaging the hardware community in the RISC-V ecosystem, and spearheading the emergence of new applications. We are constantly in awe of the brilliant minds that convene at these events. We thrive on watching intense conversations and the sharing of ideas between those already entrenched in RISC-V and others who are simply exploring design alternatives. 

The symposiums in Portland and Seattle will both feature presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners and academic luminaries. There will also be a tutorials, demos and presentations on RISC-V developments tools, platforms, core IP and SoC IP. As always, we have arranged for plenty of time for networking.

Attendance is free, but registration is required. 
We look forward to seeing you!


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