Fifteen years ago, a bold idea was forged in a university lab: what if chip design could be democratized? What if a modern, open-standard instruction set architecture (ISA) could empower engineers and innovators around the world, free from the constraints of proprietary licensing? That idea became RISC‑V, and it has since grown into a global phenomenon reshaping the future of computing.

The Origins: A Radical Vision at UC Berkeley

The story of RISC-V begins in 2010 at the Parallel Computing Laboratory (Par Lab) at UC Berkeley. Spearheaded by Professor Krste Asanović and graduate students Andrew Waterman and Yunsup Lee (who would later go on to co-found SiFive), RISC-V was born out of both necessity and vision. With support from David Patterson, the father of RISC, the team set out to build an ISA that was simple, flexible, and most importantly, open.

“We wanted to make RISC-V the standard instruction set architecture for all computing.”
– Andrew Waterman, SiFive Co-Founder & Chief Engineer

The team chose the name RISC-V (pronounced “RISK FIVE”) to signify the fifth major iteration of the RISC ISA. What made it different? RISC‑V was modular and built from a clean slate, avoiding the legacy complexity of previous versions and proprietary architectures. This modest, yet historically revolutionary new ISA could therefore scale from low-power embedded devices to high-performance datacenter workloads.

The Rise of Open Hardware

By 2015, it was clear that RISC-V had outgrown academia. That year, the RISC‑V Foundation, now RISC‑V International (or RVI for short), was formed as an independent body to guide the development of the ISA for the broader computing ecosystem. RVI is based in Switzerland, in large part to signify its neutral and independent stance as a global open standard. While RVI is an independent standards body, Krste and Andrew still hold important advisory positions and continue to work tirelessly to shape the future specifications, architecture, and vision for the future of RISC‑V. SiFive has donated a variety of technology to RISC‑V including its donation of WorldGuard security IP, along with recent donation of vector dot-product and vector-matrix extensions for AI computing. Today, RISC‑V International includes more than 4,500 members across 70 countries, from startups to tech giants.

“We believe that the ‘democratization of chip design’ enabled by RISC-V has unlocked a level of creativity and competition that was simply not possible under the old, proprietary model.”
– Yunsup Lee, SiFive Co-Founder & Chief Technology Officer

This openness has fostered unprecedented innovation. RISC-V is now present in billions of devices across industries: automotive, aerospace, mobile, embedded systems, and hyperscale data centers. Even the biggest names in tech—including all of the “Magnificent 7” (Apple, Microsoft, Amazon, Alphabet, Meta, Nvidia, and Tesla) are adopting RISC-V in various capacities.

“AI is one of the key areas accelerating adoption. RISC-V’s customization and efficiency make it the ideal foundation for the next wave of AI innovation.”
– Krste Asanović, SiFive Co-Founder & Chief Architect

SiFive: Catalyzing the RISC-V Revolution

Recognizing the commercial potential of RISC-V, the Berkeley trio co-founded SiFive in 2015—the first company dedicated to developing RISC-V-based processor IP (the blueprints that chip companies can buy to build RISC-V chips). SiFive has since become a leader in RISC-V innovation, with over 400 design wins and IP shipping into over two billion devices in the market.

Under CEO Patrick Little, who joined in 2020, SiFive has sharpened its focus on high-growth markets like automotive and AI, while pioneering scalable IP solutions that range from ultra-low-power embedded cores, through high-performance superscalar processors, to high-performance vector and matrix processors.

“RISC-V's roots were humble: in 2010, our ambitions were no more grand than designing a clean instruction-set architecture for teaching and research at Berkeley.”
– Andrew Waterman, SiFive Co-Founder & Chief Engineer

Looking Ahead: RISC-V’s Next 15 Years

RISC-V is no longer a question of “if” but “when.” Analysts and insiders alike see a world where RISC-V overtakes legacy ISAs as the default standard for computing.

“While there are now three major ISAs, I believe that within the next 15 years RISC-V will become the dominant ISA for most major computing markets.”
– Yunsup Lee

Some of this growth is being driven by two major forces: AI and Embedded. In embedded systems, RISC‑V’s power efficiency and scalability make it a clear favorite. In AI, the ability to customize hardware for specific workloads, particularly matrix and vector operations, is attracting major players.

“Vector computing is becoming more and more foundational across market segments and I believe we will continue to see strong growth in parallel computing over the next 15 years, with RISC-V firmly established as the architecture of choice in this area.”
– Krste Asanović

With AI being new, almost all hardware designs are custom, and RISC-V is being used as the base of these systems to allow customers to focus on what they do best with specialized extensions. As a result, RISC-V is being integrated into many areas of the datacenter or into edge devices for AI computing. This creates an enormous opportunity for SiFive and the RISC-V ecosystem.

"We started as an alternative to the status quo. Now we offer technical superiority in multiple domains. Our customers use customization and flexibility to go to market faster—and we deliver real software compatibility at scale.”
– Andrew Waterman

A third driver is a desire to move away from vendor lock-in. Increasing speculation in the press has raised a concern that one of the major ISA vendors will start making their own chips and compete with their customers. Companies are watching closely and almost every major company has a RISC-V program underway in case they have to react to this outcome.

A Movement, Not Just an Architecture

RISC-V is more than just an ISA — it’s a movement. It has become a symbol of engineering freedom, collaboration, and innovation. From classrooms to datacenters, RISC-V is laying the foundation for a new era of computing—one where the best ideas, not proprietary barriers, win.

As Asanović put it:
“Everyone we talk to is moving their projects and programs to RISC-V. In totality, I think the bigger question for convergence of any computing ecosystem to RISC-V is a question of when, not if.”

Want to learn more about the history of RISC-V?

Visit SiFive's history of RISC-V page to explore its journey from a student project to a global standard.

If you are interested in diving even deeper – Check out “The RISC-V Reader: An Open Architecture Atlas” book, co-authored by RISC-V co-inventor and SiFive co-founder, Andrew Waterman, available on Amazon.