The latest insights, and deeper technology dives, from RISC-V leaders

We recently announced that Intel Capital participated in our Series C funding
round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at
the Intel Capital Global Summit. 


Check out the full newsletter [here](https://info.sifive.com/the-sifive-download-part-viii)!



**Pavel Chupin, Senior Director of AI Software, SiFive**

![Birdseye view](https://images.prismic.io/sifive/aGW3H3fc4bHWi-0e_SiFive_BEVFormer_Blog_1000x500.jpg?auto=format,compress)

We’re excited to share the successful deployment of the BEVFormer model on SiFive’s Intelligence XM IP, an early access RISC-V-based AI acceleration solution. This milestone highlights the potential of open-standard hardware to handle complex perception workloads for autonomous driving.

**BEVFormer: A Proven Model, A New Challenge**

BEVFormer, introduced in 2022, is a well-established transformer-based Bird’s Eye View (BEV) perception model critical for autonomous driving. It transforms six 900x1600 camera inputs into a 200x200 BEV representation, enabling robust 3D object detection, spatial reasoning, and temporal fusion. 

![BEVFormer Image](https://images.prismic.io/sifive/aGWr4Xfc4bHWi-xL_Slide1.jpeg?auto=format,compress)

While BEVFormer itself is not new, the real accomplishment lies in bringing this sophisticated model to life on the SiFive Intelligence XM Platform, an emerging, early access RISC-V architecture. This deployment demonstrates the platform’s ability to tackle demanding AI workloads, setting a foundation for future automotive innovations.

The Power of RISC-V and SiFive’s Intelligence XM IP
Automotive AI requires compute platforms that offer high performance, customization, and power efficiency for long-lifecycle systems. Traditional proprietary processors often fall short in flexibility. RISC-V’s open-standard Instruction Set Architecture (ISA) addresses this by allowing tailored processor designs for specific workloads, such as neural inference and real-time control.

The [SiFive Intelligence XM Platform](https://www.sifive.com/cores/intelligence-xm-series), still in its early access phase, builds on this with a multi-core design featuring four X-series cores (each with a 1024-bit RISC-V vector unit) and a Matrix Engine for efficient matrix operations. Its tightly integrated architecture minimizes latency and eliminates fallback penalties common in heterogeneous systems. This enabled seamless execution of BEVFormer’s diverse modules: convolutional layers, deformable attention, and scalar operations, within a unified binary, simplifying development and boosting performance.

![SiFive XM Series](https://images.prismic.io/sifive/aGbXN3fc4bHWjCBE_Slide1.jpeg?auto=format,compress)


**Conquering Deployment Hurdles**

Running BEVFormer on early access IP was a complex endeavor, requiring innovative solutions to technical challenges. Using the SiFive AI/ML reference software stack, powered by IREE, our team enabled and implemented a few optimizations in the model for the XM Platform. Key steps included:
Model Conversion: Addressing PyTorch 1.9.1 and OpenMMLab compatibility issues to convert BEVFormer to ONNX and then to MLIR using IREE’s iree-import-onnx tool.

- Custom Operator Support: Implementing critical operators like Modulated_Deform_Conv2D and Multi_Scale_Deformable_Attention as optimized microkernels, leveraging RISC-V Vector (RVV) intrinsics for performance.

- CUDA-to-RISC-V Porting: Translating CUDA kernels to portable C/C++ and RVV code, with Large Language Models assisting in prototyping to save engineering effort.

- Matrix Engine Optimization: Mapping matrix-heavy operations (e.g., matmul) to the Matrix Engine via IREE’s mmt4d framework, ensuring hardware acceleration.

The pipeline was validated on the nuScenes dataset using QEMU emulation of the XM Platform, achieving identical accuracy to the PyTorch baseline. Visualized outputs confirmed the model’s precision in generating BEV representations, proving the platform’s capability despite its early stage.

**A Foundation for the Future**
This achievement is not about BEVFormer’s novelty but about showcasing the SiFive Intelligence XM Platform’s ability to handle complex AI workloads through SiFive AI/ML reference software stack. By successfully deploying a mature model like BEVFormer, we’ve demonstrated RISC-V’s potential to rival traditional automotive compute solutions with greater flexibility and customization.
SiFive AI/ML reference software stack, powered by IREE opens a potential for experimentation with more AI/ML models. Components, based on existing open source technologies are welcome to explore and reuse.

Our team is actively refining performance through kernel tuning and enhanced code generation. As RISC-V gains momentum in automotive AI, this milestone positions the SiFive platform as a game-changer for scalable, open-standard solutions.

**Dive Deeper and Join Us**

You can also explore the BEVFormer codebase on GitHub.

Interested in evaluating the SiFive Intelligence XM Platform or collaborating on automotive AI? SiFive has the industry’s broadest set of Automotive RISC-V solutions. [Contact us](https://www.sifive.com/contact-sales). Let’s shape the future of autonomous driving together!


SiFive_BEVFormer_Blog_1000x500.jpg

Breakthrough in Automotive AI: Running BEVFormer on SiFive’s Early Access RISC-V Intelligence XM Platform

**Ian Ferguson, VP of Vertical Markets**

I have worked with processor technology for well over 30 years. It was clear to me from the first product I worked with ([88k](https://en.wikipedia.org/wiki/Motorola_88000) from Motorola Semiconductor) that hardware was unable to make an impact on an industry without relevant, effective software support.

From my perspective, while is fair to indicate that the era of AI is reducing the ties of software to underlying hardware...or [“hardware is eating the world”](https://www.deloitte.com/ce/en/services/consulting/perspectives/hardware-is-eating-the-world.html) as some care to describe it….there is still a critical need to deliver complete, stable foundational software in order for hardware technology to flourish in a specific market and application area.

Today, [SiFive announced a collaboration with Red Hat](https://www.sifive.com/press/sifive-collaborates-with-red-hat-support-enterprise-linux-risc-v) to deliver a developer preview of [Red Hat Enterprise Linux (RHEL) 10](https://www.redhat.com/en/about/press-releases/red-hat-introduces-rhel-10) for RISC-V. The developer preview is available exclusively on our [HiFive Premier™ P550 board](https://www.sifive.com/boards/hifive-premier-p550). In essence, a Developer Preview is a way for Red Hat to engage with its community and gather valuable feedback on upcoming features before they are finalized and released as part of a supported product. This Developer Preview enables early adopters and integrators to experiment with new features and provide feedback to Red Hat. The beta of [Red Hat Enterprise Linux 10](https://www.redhat.com/en/blog/red-hat-enterprise-linux-10-beta-now-available) was released in December 2024.

With RISC-V starting with an open standards approach, the primary way of maturing a new ISA is by having a development platform that hardware and software developers can use.  As a participant in the open-source communities that strive to enable solutions to customer problems and business needs, Red Hat understands that some members of the ecosystem will naturally gravitate to Fedora and CentOS STREAM and the rapid innovation they deliver, while others are interested in a slightly slower pace for other parts of the ecosystem.

I feel that Red Hat’s decision to start their hardware integration with SiFive sends a clear message about the quality, performance and technical support that this board provides. That said, it is also important to give a shout out to the significant impact of the open-source community, particularly those invested in the [RISE Project](https://riseproject.dev), for their work to continue to port, optimize and upstream the critical pieces of RISC-V enabling code that are making this market-disrupting milestone a reality. 

This highly anticipated software is immediately available. Red Hat staff is showcasing the software running on the P550 at this week’s Red Hat Summit in Boston where customers, partners and analysts can view a hands-on demonstration. It is a non-trivial decision to embark on a path to support a new processor architecture, and I view this as an important commitment that supports the growing importance and acceptance of RISC-V for high-performance use cases.

In many ways, this is not the end of the journey, it is the start. There is much foundational work still to be done by SiFive, Red Hat, other RISC-V members as well as in the broader open-source community.  This work will ultimately enable RISC-V to compete on a level playing field with incumbent architectures in the Enterprise server market. Today’s announcement with Red Hat is a massive step forward and the SiFive team is eager to continue to contribute in doing its part on the journey ahead.

**May 22 update**

I mentioned above about the linkages between Red Hat software and other distributions. Within a day of the announcement of our collaboration with Red Hat, there were three important updates: 

1) A [blog post](https://blog.centos.org/2025/05/initial-centos-support-for-risc-v/) as issued on the CentOS community page outlining plans for RISC-V support

2) Rocky Linux [announced](https://rockylinux.org/news/rockylinux-support-for-riscv) intent to add RISC-V images to their distribution

3) On the public Fedora channel, Alma also claimed: "FWIW AlmaLinux will be supporting it with 10 too, we're just not making flashy blog posts about it."

All of this activity will provide more options for developers, inspiring innovation and creating highly differentiated platforms for the end customer base.




Red Hat Brings Their Enterprise Linux On SiFive Hardware

SiFive_redhat-launch_Blog_1000x500.jpg

Red Hat Brings Their Enterprise Linux On SiFive Hardware!

Fifteen years ago, a bold idea was forged in a university lab: what if chip design could be democratized? What if a modern, open-standard instruction set architecture (ISA) could empower engineers and innovators around the world, free from the constraints of proprietary licensing? That idea became RISC‑V, and it has since grown into a global phenomenon reshaping the future of computing. 

## The Origins: A Radical Vision at UC Berkeley
 
The story of RISC-V begins in 2010 at the Parallel Computing Laboratory (Par Lab) at UC Berkeley. Spearheaded by Professor Krste Asanović and graduate students Andrew Waterman and Yunsup Lee (who would later go on to co-found SiFive), RISC-V was born out of both necessity and vision. With support from David Patterson, the father of RISC, the team set out to build an ISA that was simple, flexible, and most importantly, open. 

“We wanted to make RISC-V the standard instruction set architecture for all computing.”
 – Andrew Waterman, SiFive Co-Founder & Chief Engineer
 
The team chose the name RISC-V (pronounced “RISK FIVE”) to signify the fifth major iteration of the RISC ISA. What made it different? RISC‑V was modular and built from a clean slate, avoiding the legacy complexity of previous versions and proprietary architectures. This modest, yet historically revolutionary new ISA could therefore scale from low-power embedded devices to high-performance datacenter workloads. 

## The Rise of Open Hardware

By 2015, it was clear that RISC-V had outgrown academia. That year, the RISC‑V Foundation, now RISC‑V International (or RVI for short), was formed as an independent body to guide the development of the ISA for the broader computing ecosystem. RVI is based in Switzerland, in large part to signify its neutral and independent stance as a global open standard. While RVI is an independent standards body, Krste and Andrew still hold important advisory positions and continue to work tirelessly to shape the future specifications, architecture, and vision for the future of RISC‑V. SiFive has donated a variety of technology to RISC‑V including its donation of WorldGuard security IP, along with recent donation of vector dot-product and vector-matrix extensions for AI computing. Today, RISC‑V International includes more than 4,500 members across 70 countries, from startups to tech giants. 

“We believe that the ‘democratization of chip design’ enabled by RISC-V has unlocked a level of creativity and competition that was simply not possible under the old, proprietary model.”
 – Yunsup Lee, SiFive Co-Founder & Chief Technology Officer

This openness has fostered unprecedented innovation. RISC-V is now present in billions of devices across industries: [automotive](https://www.sifive.com/solutions/automotive), [aerospace](https://www.sifive.com/solutions/aerospace-defense), mobile, [embedded systems](https://www.sifive.com/solutions/iot-embedded), and [hyperscale data centers](https://www.sifive.com/solutions/data-center). Even the biggest names in tech—including all of the “Magnificent 7” (Apple, Microsoft, Amazon, Alphabet, Meta, Nvidia, and Tesla) are adopting RISC-V in various capacities. 

“AI is one of the key areas accelerating adoption. RISC-V’s customization and efficiency make it the ideal foundation for the next wave of AI innovation.”
 – Krste Asanović, SiFive Co-Founder & Chief Architect 

## SiFive: Catalyzing the RISC-V Revolution
 
Recognizing the commercial potential of RISC-V, the Berkeley trio co-founded SiFive in 2015—the first company dedicated to developing [RISC-V-based processor IP](https://www.sifive.com/risc-v-core-ip) (the blueprints that chip companies can buy to build RISC-V chips). SiFive has since become a leader in RISC-V innovation, with over 400 design wins and IP shipping into over two billion devices in the market.

Learn more about the [SiFive business model](https://www.sifive.com/about/business-model).

Under CEO Patrick Little, who joined in 2020, SiFive has sharpened its focus on high-growth markets like automotive and [AI](https://www.sifive.com/solutions/ai-ml), while pioneering scalable IP solutions that range from ultra-low-power embedded cores, through high-performance superscalar processors, to high-performance vector and matrix processors. 

“RISC-V's roots were humble: in 2010, our ambitions were no more grand than designing a clean instruction-set architecture for teaching and research at Berkeley.”
 – Andrew Waterman, SiFive Co-Founder & Chief Engineer 

## Looking Ahead: RISC-V’s Next 15 Years
 
RISC-V is no longer a question of “if” but “when.” Analysts and insiders alike see a world where RISC-V overtakes legacy ISAs as the default standard for computing. 

“While there are now three major ISAs, I believe that within the next 15 years RISC-V will become the dominant ISA for most major computing markets.”
 – Yunsup Lee 

Some of this growth is being driven by two major forces: AI and Embedded. In embedded systems, RISC‑V’s power efficiency and scalability make it a clear favorite. In AI, the ability to customize hardware for specific workloads, particularly matrix and vector operations, is attracting major players. 

“Vector computing is becoming more and more foundational across market segments and I believe we will continue to see strong growth in parallel computing over the next 15 years, with RISC-V firmly established as the architecture of choice in this area.”
 – Krste Asanović 

With AI being new, almost all hardware designs are custom, and RISC-V is being used as the base of these systems to allow customers to focus on what they do best with specialized extensions. As a result, RISC-V is being integrated into many areas of the datacenter or into edge devices for AI computing. This creates an enormous opportunity for SiFive and the RISC-V ecosystem. 

"We started as an alternative to the status quo. Now we offer technical superiority in multiple domains. Our customers use customization and flexibility to go to market faster—and we deliver real software compatibility at scale.”
 – Andrew Waterman 

A third driver is a desire to move away from vendor lock-in. Increasing speculation in the press has raised a concern that one of the major ISA vendors will start making their own chips and compete with their customers. Companies are watching closely and almost every major company has a RISC-V program underway in case they have to react to this outcome. 

## A Movement, Not Just an Architecture
 
RISC-V is more than just an ISA — it’s a movement. It has become a symbol of engineering freedom, collaboration, and innovation. From classrooms to datacenters, RISC-V is laying the foundation for a new era of computing—one where the best ideas, not proprietary barriers, win. 

As Asanović put it: 
“Everyone we talk to is moving their projects and programs to RISC-V. In totality, I think the bigger question for convergence of any computing ecosystem to RISC-V is a question of when, not if.” 
 
## Want to learn more about the history of RISC-V?
 
Visit SiFive's [history of RISC-V](https://www.sifive.com/about/risc-v-history) page to explore its journey from a student project to a global standard. 

If you are interested in diving even deeper – Check out [“The RISC-V Reader: An Open Architecture Atlas”](https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas/dp/0999249118/ref=sr_1_4?crid=18FP9Y74E6A4E&dib=eyJ2IjoiMSJ9.sw4Ya06cgKAUHpb5OPY9kurjhIYa3AXZop39N148J7_xHF8jn1GwhiVWPUV3uMG2uN1qucPofCMuxTNr6amcYuthNAY1bR7Aln5sgBeQzyjOtky91RoSlcSSFzGoM4aqJbV9PjaYSFEd4buXm8_zh4fSFuiMEPD9VuIrx6zhTga_aUoUVJvbgqu-kKdjMtibgqxeRbz0xNyQSJLiYrrIFP7CQnbIYgyq1XsLW0dZrHxsPQQRGnDodG0ScSgxUxYf0MzZU28Mt_IplVJ30_W56yIeP9DyHr-U1rFpSJj2IBM.kZmKr7v2255jQXt8tdv6-jwRriWa00M6_NzITJdbBho&dib_tag=se&keywords=risc-v&qid=1747575517&sprefix=risc-v%2Caps%2C274&sr=8-4) book, co-authored by RISC-V co-inventor and SiFive co-founder, Andrew Waterman, available on Amazon.

Fifteen years ago, a bold idea was forged in a university lab: what if chip design could be democratized? What if a modern, open-standard instruction set architecture (ISA) could empower engineers and innovators around the world, free from the constraints of proprietary licensing? That idea became RISC‑V, and it has since grown into a global phenomenon reshaping the future of computing.

From Berkeley Lab to Global Standard: RISC‑V’s 15-Year Journey

banner-xm.jpg

**Dev Mandya, Senior Director, Strategic Business Development for SiFive** 

The storage market was among the earliest to recognize and embrace the value proposition of the RISC‑V architecture. At the heart of this shift was the appeal of an open standard — one that offered a faster track to innovation while helping to address potential supply chain risks. RISC-V also empowered companies to create and deploy custom instructions tailored to accelerate specific algorithms. 

Given that [storage systems](https://www.sifive.com/solutions/storage) often function as “black boxes” running proprietary software, this flexibility opened the door to building optimized hardware solutions for tasks such as wear leveling and encryption—achieving performance gains without fragmenting the broader software ecosystem, and RISC-V has been racing to keep pace. 

The world of SSDs is evolving at record speed. In 2025, not only are we seeing a leap in raw performance, but also a transformation in how storage is architected, managed, and optimized for new workloads like AI, gaming, and cloud computing. SiFive, the RISC-V pioneer, is at the heart of this shift — delivering flexible, efficient, and secure processor IP that aligns perfectly with the latest trends in SSD controller design. 

 

## SSD Controllers in 2025: What’s New?

- **Blazing Speeds with PCIe Gen5**

The latest generation SSD controllers are smashing through speed barriers and are built on advanced technology nodes, allowing them to deliver high read/write speeds, up to 14.5 GB/s and random IOPS in the millions—ideal for AI, high-performance gaming, and data center workloads. These controllers support multiple NAND channels and the newest NVMe 2.0 protocol, ensuring high throughput and low latency for demanding applications. 

**Read more:** [DIGITIMES: Storage giants collaborate with Silicon Motion Technology](https://www.digitimes.com/news/a20250121PR200/ces-2025-silicon-motion-pcie-performance.html&chid=9)
 
- **Efficiency and Power Optimization** 

With power budgets tighter than ever, the new SSD controllers are engineered for efficiency and cut power consumption by up to 50% compared to previous generations. Some of the new designs are bringing Gen5 performance to more affordable, energy-conscious devices, making high speeds accessible for notebooks and mainstream users.
 
- **AI and Computational Storage**

AI is no longer just a buzzword in storage. Modern SSD controllers are being designed to handle AI-driven workloads and in-storage processing. This means SSDs are starting to process data directly—whether it’s pre-processing, encryption, or even running ML inference—reducing bottlenecks and accelerating analytics at the edge and in the cloud. 

- **Security and Reliability** 

Controllers now offer enhanced security features like secure boot, AES 128/256 encryption, TCG Opal 2.0 compliance, and advanced ECC—critical for both enterprise and consumer markets. 

**Read more:** [Micron: The value of Crucial hardware encryption](https://www.crucial.com/support/hardware-encryption)

 

## How SiFive’s RISC-V Solutions Fit the New SSD Landscape

[SiFive’s RISC-V portfolio](https://www.sifive.com/risc-v-core-ip) is purpose-built for these new realities:
 
- **Configurability and Scalability**: SiFive provides a highly configurable and scalable portfolio of processor cores, ranging from the compact and efficient [SiFive Essential™ family](https://www.sifive.com/cores/essential) cores like the E2, to mid-range, single-issue, multi-core E6 options ideal for back-end control. For demanding workloads, SiFive also offers high-performance, multi-core, dual-issue 32-bit E7, 64-bit S7, and MMU-supported U7 cores, as well as advanced 64-bit Out-of-Order Performance cores designed for front-end compute and AI acceleration. This broad portfolio enables SSD designers to tailor solutions that address the full spectrum of requirements—from cost-sensitive consumer-class devices to robust, enterprise-class, multi-channel controllers. 

![Essential Family](https://images.prismic.io/sifive/aCUb6idWJ-7kSISG_essentials.png?auto=format,compress)
 
- **Performance and Power**: Our latest Essential Gen4 cores deliver up to 40% lower runtime power and improved code density compared to previous generation cores, featuring advanced power management technologies such as fine-grained clock gating and DVFS. These enhancements mirror the efficiency gains seen in the latest commercial SSD controllers. There is a strong focus on energy efficiency for storage solutions in consumer platforms like smartphones. In the enterprise segment, the demands of PCIe Gen6 are driving companies to seek higher-performance processors with multi-issue, out-of-order pipelines. [SiFive Performance™ family](https://www.sifive.com/cores/performance) cores are well-suited to meet these emerging requirements for next-generation SSD controllers. 
 
- **Security and Reliability**: SiFive cores support secure boot, hardware encryption, and advanced error correction, meeting the stringent requirements of modern SSDs. 
 
- **AI and Computational Storage Ready**: [SiFive Intelligence™ family](https://www.sifive.com/cores/intelligence) cores (X280, X380) are designed for computational storage, enabling real-time analytics and ML workloads directly at the storage layer—perfect for the AI-driven future of storage. 

 
 
## Real-World Impact: Customer Success
 
SiFive’s technology has demonstrated significant real-world benefits in the SSD market. For example, [FADU](https://www.fadu.io), a leading storage solution provider, achieved up to 30% lower power consumption, a smaller die size, and three to four times greater IOPS per watt by utilizing SiFive’s Essential cores in its Annapurna SSD controller and Bravo Series Enterprise SSD. These improvements enabled FADU to maximize efficiency and effectively balance the trade-offs between power and performance, highlighting the tangible advantages of adopting SiFive’s solutions. FADU has harnessed a range of Essential cores including the E2, E5 and S5, for different generations of SSD platforms.

**Read more:** [FADU Launches Industry Leading SSD Solutions Powered by SiFive RISC-V Core IP](https://www.prnewswire.com/news-releases/fadu-launches-industry-leading-ssd-solutions-powered-by-sifive-risc-v-core-ip-300693176.html)

![Fadu Products](https://images.prismic.io/sifive/aCUb6ydWJ-7kSISH_fadu.png?auto=format,compress)
 
 
In addition to this success, SiFive’s processor cores have been adopted and evaluated by leading storage solution providers worldwide. Companies across multiple regions are choosing SiFive’s Essential and other advanced cores for both current and next-generation SSD controller architectures. This underscores our proven production track record, robust technical support, and the ability to meet diverse requirements in consumer and enterprise storage markets. 
SiFive’s strong collaboration with FADU on their storage products has been developing since 2017, and since then, FADU has adopted a range of our Essential products as the foundation of their product lineup. More details about this collaboration and recent product reviews that demonstrate the competitiveness of FADU’s enterprise SSDs can be found on their respective sites. 

 

## The Bottom Line
 
The SSD controller market is in the midst of a revolution—driven by the need for speed, efficiency, intelligence, and security. With the latest PCIe Gen5 controllers delivering record-breaking performance and energy efficiency, and with AI workloads moving closer to the data, the architecture inside your SSD matters more than ever. 

SiFive’s RISC-V solutions are uniquely positioned to meet these challenges, offering unmatched configurability, proven efficiency, and future-ready AI capabilities. Whether you’re building SSDs for the cloud, the edge, or the next gaming powerhouse, SiFive is helping storage innovators stay ahead of the curve—one core at a time. 

If you’d like more information on how we can help you meet your storage challenge, [contact us via this form](https://www.sifive.com/contact-sales) or email [storagesolutions@sifive.com](mailto:storagesolutions@sifive.com).

Discover how SiFive’s RISC-V processor IP is transforming SSD controller design in 2025—powering faster, more efficient, secure, and AI-ready storage solutions for cloud, edge, and consumer markets.

SiFive Storage Solutions: Powering the Next Generation of SSD

solutions-storage-spot.jpg

**Martyn Stroeve, VP, Marketing SiFive**

### From Yocto to Fedora, the HiFive P550 isn’t just powering code—it’s powering a movement

The SiFive HiFive Premier P550 is a powerful showcase for what high-performance RISC-V hardware can achieve, and it’s rapidly becoming the reference point for Linux distribution support across the RISC-V ecosystem. Whether you're a kernel hacker, a distro maintainer, or an embedded developer, the HiFive Premier P550 offers a stable, feature-rich platform to build, test, and deploy Linux-based software. This type of foundational hardware is helping to move the RISC-V ecosystem from potential to production.

**Why Development Boards Are Key to Linux Support**

Mainline Linux support doesn't happen in a vacuum. Developers using distributions such as Debian, Ubuntu, and Fedora, along with build systems like Yocto, need a reliable, open platform to validate software, run CI tests, and get real feedback from users. Development boards are where the ecosystem meets reality.
The HiFive Premier P550 fills that role perfectly. It’s the bridge between IP core and OS image, helping to validate compilers, test drivers, and tune performance at scale. 

**Collaborating with Red Hat to Support Red Hat Enterprise Linux for RISC-V**

(May 20 update) We have announced a collaboration with Red Hat, the world’s leading provider of enterprise open source solutions, to bring Red Hat Enterprise Linux support to the rapidly growing RISC-V community. Red Hat Enterprise Linux 10 is available in developer preview on the SiFive HiFive Premier™ P550 platform.

**Read the news:** [SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
](https://www.sifive.com/press/sifive-collaborates-with-red-hat-support-enterprise-linux-risc-v) 
**Read the blog post:** [Red Hat Brings Their Enterprise Linux On SiFive Hardware!](https://www.sifive.com/blog/red-hat-enterprise-linux-on-sifive-hardware)

**Yocto: The Customizable Starting Point**

Yocto is often the first step in getting Linux running on new hardware, and the HiFive Premier P550 is no exception. Through projects like meta-sifive, developers can build custom Linux images tailored to their exact needs.

This flexibility is essential for early adopters and embedded developers who want to control every aspect of their OS stack. With Yocto, the HiFive Premier P550 becomes a sandbox for low-level tuning, BSP bring-up, and rapid prototyping.

**Ubuntu: Mainstream Developer Appeal**
 
SiFive is collaborating with Canonical, the publisher of Ubuntu, to ensure that developers can smoothly run the Linux distribution on the HiFive Premier P550. With Canonical Ubuntu 24.04 pre-installed on the HiFive Premier P550, developers get access to a familiar, user-friendly environment complete with snap packages, apt tooling, and cloud-native workflows to help streamline development and accelerate time to market. Thanks to its Ubuntu support, HiFive Premier P550 provides an approachable platform for machine learning, robotics, and AI experimentation—all backed by a globally trusted distribution. 

Gordan Markuš, Director of Silicon Alliances at Canonical, explained why this board is such a big deal: “The HiFive Premier P550 stands out as the premium development board for enthusiasts and developers, helping drive the next wave of cutting-edge RISC-V development. We’re proud to see Ubuntu Linux as a key enabler of this innovation and development on the Premier P550 board.”

Ubuntu is free to use and comes with five years of free security maintenance for the operating system. Developers and innovators can rely on Ubuntu’s stable and secure platform to access the open source software ecosystem and get access to bug fixes and security updates for 10+ years backed by Canonical’s enterprise-grade support. 

**Debian: Upstream Credibility and Stability**

Debian support is also important for many developers. Getting the HiFive Premier P550 running under Debian means tackling kernel patching, upstreaming drivers, and ensuring long-term package compatibility.

Because so many downstream projects depend on Debian (including Ubuntu), this support is critical for the RISC-V ecosystem. Debian support also builds confidence in the HiFive Premier P550 as a stable base for long-lived applications and research.

**Fedora: Cutting-Edge Innovation**

Fedora is known for its forward-looking architecture support and rapid evolution. When Fedora lands on a platform, it’s a strong signal that the hardware is ready for prime time.

With Fedora running on the HiFive Premier P550, developers have access to modern developer tools, the latest kernels, and an ecosystem geared toward innovation. It’s a perfect match for those pushing the boundaries of what’s possible with RISC-V.

**The Bigger Picture: The HiFive Premier P550 as the RISC-V Linux Hub**

All these capabilities prove that the HiFive Premier P550 is more than a development board—it’s a software platform. One that the Linux world is converging around.

From embedded Yocto builds to full-featured Fedora desktops, the HiFive Premier P550 is helping Linux developers at every level get hands-on with RISC-V, build real systems, and upstream their work.


**Get Involved**

Want to try these distros yourself and contribute to the ecosystem? Here's how to get started:


- [HiFive Premier P550 product page](https://www.sifive.com/boards/hifive-premier-p550)

- [meta-sifive on GitHub](https://github.com/sifiveinc/meta-sifive)

- [Ubuntu RISC-V Community Page](https://discourse.ubuntu.com/c/documentation/risc-v-docs/83)

- [Debian RISC-V Wiki](https://wiki.debian.org/RISC-V)

- [Fedora RISC-V Tracker](https://gitlab.com/abologna/fedora-riscv-tracker)

Whether you're debugging a kernel, packaging an app, or writing a blog of your own, the HiFive Premier P550 is the ideal platform.

SiFive Data Center Innovation

Leadership in Embedded Markets

Essential Family

Intelligence Family

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