The latest insights, and deeper technology dives, from RISC-V leaders

We recently announced that Intel Capital participated in our Series C funding
round! Our CEO, Naveed Sherwani, revealed the investment earlier this month at
the Intel Capital Global Summit. 


Check out the full newsletter [here](https://info.sifive.com/the-sifive-download-part-viii)!


The Accelerator Control Unit (ACU) is a popular use case for our new Intelligence products, learn why in this in depth look.

 **Using SiFive’s X100-series as an Accelerator Control Unit (ACU)** 
 
In Pete Lewin’s previous blog post, [The Perfect Solution for Local AI
](https://www.sifive.com/blog/the-perfect-solution-for-local-ai), he introduced some of the high-level thinking behind the creation of the [SiFive Intelligence X100 product series](https://www.sifive.com/cores/intelligence-x100-series) and showed a performance comparison against an established incumbent. He, and I, discussed the rapid pace of innovation in the AI market and how that is making it incredibly challenging to design the “perfect” hardware accelerator. Instead, what we are seeing from customers is a desire to complement the accelerator with a programmable front end; what we term an accelerator control unit (ACU). This allows them to focus more of their efforts (and R&D spending) on the data-processing capabilities of the accelerator rather than control and management functions, which SiFive’s RISC-V-based approach does so well.  

In this blog, I dive a little deeper into the options to efficiently couple a processor from the X100 series to a hardware accelerator. The diagram below highlights how customers are using X-series products as Accelerator Control Units (ACUs). 

The integrated vector engine present in the X160 and X180 processors provides complementary compute capabilities that can also assist the accelerator in a range of tasks, including pre-/post-formatting of data and handling of corner cases. Basing this system capability on a product that is 100% compatible with the RISC-V instruction set architecture enables customers to select from a broad, and rapidly expanding set of application software, operating systems and development tool options. 
 
  ![Accelerator Control Unit diagram](https://images.prismic.io/sifive/aM2P6J5xUNkB06qA_diagramblog1.png?auto=format,compress)

Harnessing the X100 provides a standardized software development model for two different types of proprietary SiFive direct-to-core accelerator attachments which lower latency and improve overall performance.
  
- **SiFive Scalar Coprocessor Interface (SSCI)**: New with Intelligence Gen 2, this interface allows the accelerator to be driven via RISC-V custom instructions with direct access to the registers within the X100 processor. Our customers are using this to control and configure a tightly coupled coprocessor. 

- **Vector Coprocessor Interface (VCIX)**: A high-bandwidth interface to support data movement to a matrix coprocessor. Using VCIX provides high-bandwidth access to CPU vector registers, lowers latency, and uses vector-type instruction formats to feed customers matrix engines with large datasets. This isn’t just for edge/IoT, VCIX is also being used in this way by large data center customers. 
 
There is also the Core Local Port (CLP) that allows fast access to accelerator SRAM for companion compute on the CPU. 
 
How does this work in practice? If we assume a SSCI-type of connector, the custom function might be something such as performing trigonometric functions, algorithm-specific bit manipulation or math functions, such as square root. 
 
![Diagram](https://images.prismic.io/sifive/aM2P6Z5xUNkB06qB_daigramblog2.png?auto=format,compress)

The custom logic only has to decode a few bits of the opcode and perform the actual operation being implemented. The existing CPU logic in the X100 handles the full decode of the instruction, selecting the source register, reading/writing from/to a destination register, performing data forwarding and managing pipeline stall / flush functions.  

Are you wrestling with creating the optimal system architecture for a next-generation platform? Tasked with bringing AI to your IoT workloads? The [SiFive Intelligence Family](https://www.sifive.com/cores/intelligence) was designed for AI and is a popular solution for a growing number of applications and could be your perfect solution. SiFive can help with modeling tools and free system architecture reviews to de-risk and accelerate your program. 

Check out this case study to see how customers are already putting these new products to work:<br>
[Tier 1 US Semiconductor Company Licenses SiFive X160 for Industrial MCU Applications](https://www.sifive.com/document-file/x160-accelerator-control-unit-use-case-study).

**Author**

Ian Ferguson is the Vice President of Vertical Markets and Business Development at SiFive, where he is responsible for accelerating growth of the company across a range of growth segments including data centers, consumer and automotive market segments. Of particular focus is how artificial intelligence offers an opportunity for industries to shift from incumbent architectures to the RISC-V open standard. Prior to joining SiFive Ian worked at Lynx Software Technologies as the vice president of marketing at Lynx Software Technologies, responsible for all aspects of the outward-facing presence of the company to its customer, partner, press and analyst communities. Ian was a key part of the team that was responsible for selling the company to OceanSound Partners, a private equity firm. Ian also spent nearly 11 years at Arm, where he held various roles leading teams in vertical marketing, corporate marketing and strategic alliances. Ian is a graduate of Loughborough University (UK) with a bachelor’s degree in electrical and electrical engineering.
  


Why are Accelerator Control Units becoming so popular? SiFive explains the growing use of RISC-V Intelligence Family products to create more Intelligent Accelerators from the edge to the cloud

Building the Future of AI with SiFive X100 as an Accelerator Control Unit (ACU)

diagram blog 1.png

Building the Future of AI on Intelligent Accelerators 

Away from the performance headliners and press articles about the cloud industry, there is a vast opportunity for tinyML at the far edge.  This is a diverse collection of sensor-rich endpoints that collect, pre-process, and analyze real-world data prior to submitting metadata to the cloud. Learn about how SiFIve products are driving innovation across this space.


**SiFive’s X100-Series, Part of the Second Generation SiFive Intelligence Family**

Right now, there is a massive focus on “up and to the right” hardware technologies that can push AI performance levels to new heights for data centers. During the HotChips 2025 conference, the thirst for improved performance in hyperscalers seemed to drive the vast majority of the agenda, as the big, powerful chips stole the spotlight.

Yet, away from the performance headliners and press articles about the cloud industry, there is a vast opportunity for tinyML at the far edge.  This is a diverse collection of sensor-rich endpoints that collect, pre-process, and analyze real-world data prior to submitting metadata to the cloud.  This graph forecasts the fast-growing AI workloads that will be run in edge, mobile, PC, and IOT systems markets. 

![graph](https://images.prismic.io/sifive/aMM5K2GNHVfTPEW__graphforblog.png?auto=format,compress)

The reason behind this growth is simple: not all AI tasks can or should be done in the cloud or a large datacenter.  Massive opportunities exist where there is inadequate internet access, need for real-time responsiveness, and a need for privacy that prevents cloud-based solutions that have network dependencies, data latencies, and security/privacy concerns. Even if cloud-based solutions are used, the ability to do AI locally reduces data movement costs and power consumption and is more sustainable. While other IP suppliers have “paused” their product developments for this set of use cases, SiFive is doubling down and investing heavily in broadening its offering for the diverse set of use cases at the far edge and complementing those processors with reference AI software stacks. The focus here is on enabling our customers to create and deploy leadership products for their areas of focus in the most cost- and time-effective way.

![AI models effectiveness](https://images.prismic.io/sifive/aMM5LGGNHVfTPEXA_slideforblog.png?auto=format,compress)
 
**What does it take to bring efficient AI to the edge?**
 
With the pace of innovation of AI models (with convolutional neural networks being replaced with transformer models, and some industry experts already predicting the death of those), building a flexible architecture that can adapt is key.  To enable AI everywhere, the companies developing products for edge use cases are focused on improving latency, optimizing usage of bandwidth, and enhancing data security. These systems are typically faced with intensive resource constraints, including power, cost, and size.  Many vertical markets have additional unique needs: in healthcare, complying with data privacy laws is paramount; in industrial and manufacturing sites, real-time responsiveness is crucial; in automotive, connectivity is not guaranteed.

The industry uses a wide range of names for this broad set of applications, with one of the more recent ones being “Physical AI”. Whatever market categorization is used, at SiFive, we embrace Local AI and are showing why harnessing open-standard RISC-V as the foundation of these systems is the best solution for these applications - with advantages in power, size and common software. Starting with just one product in 2021, the first generation of our Intelligence product family has become very popular, with over 40 design wins across a diverse set of IoT applications. To meet increasing and broader market demand, the 2nd generation Intelligence products launched officially today.  The combination of dedicated scalar and vector pipelines in our new Intelligence products provides our customers choice, scalability and an opportunity to innovate in the creation of accelerated compute solutions. The smallest of these, the [new X100-series](https://www.sifive.com/blog/the-perfect-solution-for-local-ai) were designed based on direct feedback from customers about the need for more efficient AI inference at the deeply embedded edge.

![AI products chart](https://images.prismic.io/sifive/aMM5KmGNHVfTPEW-_blog3.png?auto=format,compress)

Our products do not just operate as standalone processors but can be paired with customer accelerators.  While specialized accelerators can deliver great performance and efficiency, the accelerator function is fixed and can be limited. As SiFive co-founder Krste, mentions in his [product launch video](https://www.youtube.com/watch?v=_oTL_8IV5Ho), one of our key advantages with the Second Generation Intelligence family, is to enable the creation of ‘intelligent accelerators’, combining powerful fixed function accelerators with a programmable front end. This is accomplished by incorporating two direct-to-core interfaces specifically designed for data movement and control functions. 

Another aspect of AI is the datatype support. With all second gen Intelligence products, we now have support for Bfloat16; originally developed by Google Brain, Bfloat16 was designed specifically for the needs of neural network training and inference. Importantly, this data type allows AI inference to achieve a level of accuracy comparable to the standard 32-bit format while reducing memory usage and speeding up computations. This is an example of a function that has only recently started being deployed at scale and, therefore, isn’t supported on many legacy products. While I focus here on the capabilities in the Second Generation of the Intelligence Family, you can imagine that SiFive is actively tracking other industry standards and proposals about data types and engaging with customers to determine the future direction of this product family.

There are two members of the X100 product series at this point, the [X160](https://www.sifive.com/document-file/sifive-intelligence-x160-gen2-product-brief) and [X180](https://www.sifive.com/document-file/sifive-intelligence-x180-gen2-product-brief). The latter is a 64-bit processor. One piece of early customer feedback was that it would typlically be paired with a 64-bit host processor (typically running Linux). Use of the X180 simplifies the memory map and sharing of information between the cores.  

So, what does all this mean for vertical markets that are developing and adopting Local AI solutions?  Dedicated vector processing in small form factors means AI workloads can be run faster, and with less power, ultimately enabling more diverse solutions that deliver real-time responses with enhanced privacy, without requiring network connectivity.  Having the option of a single scalable architecture that can span the breadth of edge AI applications makes product development and software programming much simpler.  Product roadmaps can be future-proofed for the rapidly changing AI model landscape as customized instructions can be added.  Instead of being restricted to limited processor options and siloed software stacks, the RISC-V open standard means your product engineers can think big about tinyML.

The opportunity is so great, and the advantages so compelling that, even before being launched, the products have already been licensed by two top tier US semiconductor manufacturers to build into their future edge AI SoCs.   You can read more on these case studies [here](https://www.sifive.com/document-file/x160-standalone-vector-cpu-case-study), and you can read more details about the [X100 product series](https://www.sifive.com/cores/intelligence-x100-series).  

If you want to discuss how SiFive products can be part of your company’s AI journey, please [contact us](https://www.sifive.com/contact-sales). 

Ian Ferguson, VP Vertical Markets at SiFive

Blog describes AI products from SiFIve driving innovation at the far edge of AI compute

SiFive_intelligence-gen2_Blog2_1000x500 (1).jpg

SiFive's new Intelligence X100 Series brings exciting performance improvements critical for AI at the far edge to the data center.

**The New X100 series; Part of the 2nd generation SiFive Intelligence Family**

There has been significant focus in the tech industry over recent years on AI. With the fast growth of RISC-V, SiFive has taken the lead through our Intelligence family of IP, offering a single ISA-based scalable compute platform and the ability to customize to specific AI workloads. 

One request we often get from our customers is for help in moving AI capabilities from the cloud into factories, into people’s homes and offices, and into their hands – making AI local. There are several reasons why they want to do this. Firstly, processing data locally can give much quicker responses, making interacting with a device seem far more natural. It also helps ensure privacy and protection of your data – if that data never leaves your local device, it’s much easier to know who has access to it and what they do with it.  As we come to rely on this technology more, it also becomes important to know that it will work reliably, even when you can’t rely on network connectivity or infrastructure availability.

Achieving this is not straightforward, however. AI typically requires large amounts of data, and intensive compute power. Existing embedded processors often do not provide sufficient data processing capabilities, and the cost and power constraints of these devices do not allow more powerful CPUs designed for the datacenter to be used. SiFive’s new X100 series addresses these challenges in several key ways. 

Firstly, we have scaled down the vector engine used on our X200 and X300 series to fit the stringent cost and power constraints, while still providing the data processing performance required for many edge-AI inference use cases. The RISC-V vector ISA and a range of clever implementation features have resulted in a flexible vector engine that can address these challenges even with low cost, high latency memory (a future blog post will delve into these features in more technical detail). 

The combined result of these features, however, is that a SiFive X160 based design can perform many AI inference tasks at over twice the speed of the Arm™ Cortex®-M85, with the same silicon footprint.

![SiFive vs. Arm Chart](https://images.prismic.io/sifive/aL2oqGGNHVfTOvXU_figure1.png?auto=format,compress)
**Figure 1: SiFive Intelligence X160 performance vs competition in typical AI tasks.** 

Some edge AI tasks however will require more performance, and this can only be realized within the cost and power budgets of edge devices by adding custom accelerators. These allow our customers to provide just the right compute profile for the intended task, within the smallest area and power constraints. However, integrating such accelerators into a complex compute subsystem can be difficult and inefficient from both a hardware and software perspective. To assist in this task and improve efficiency, we’ve provided two different direct-to-core coprocessor interfaces that can be used individually or together, depending on the end applications requirements. This allows the X100 series to be used as an Accelerator Control Unit (ACU), where it can take on the detailed management and partnership with a customer's custom acceleratoe, another area that will be explored in detail in a future blog post.

Although only recently introduced, we have a number of customers already working hard on integrating the X100 series into their systems to benefit from this unrivaled AI efficiency. Two of these are Tier 1 US semiconductor companies, one leveraging the vector performance of X160 to power their next-gen Edge AI SoCs, and the other using X160 as control and assist for their own custom AI accelerator.

In addition to the X160, we have also released the X180. This Intelligence IP implements the 64-bit RV64I ISA. The larger physical address space makes this ideal for working alongside larger CPUs in a complex SoC.

![SiFive Intelligence 160 diagram](https://images.prismic.io/sifive/aL2op2GNHVfTOvXS_fig2.png?auto=format,compress)
![SiFive Intelligence 180 diagram](https://images.prismic.io/sifive/aL2op2GNHVfTOvXT_fig21.png?auto=format,compress)       
**Figure 2: Introducing the SiFive Intelligence X100-series products: X160 and X180**

These new products are ideal for supporting on-device Local AI, inference at the edge and vector processing at the deeply embedded far edge.  To learn more about these products, review their specs and read about customer and vertical use cases, please take a look at the [Intelligence Family webpage](https://www.sifive.com/cores/intelligence) and download our product briefs **[X160](https://www.sifive.com/document-file/sifive-intelligence-x160-gen2-product-brief)**, **[X180](https://www.sifive.com/document-file/sifive-intelligence-x180-gen2-product-brief)**, or the **[Intelligence Family](https://www.sifive.com/document-file/sifive-intelligence-gen2-family-brief)**.  

If you are working on a Local AI solution, and want to explore if these, or any other SiFive products are a good fit, please contact our [SiFive sales team](https://www.sifive.com/contact-sales).  





SiFive's new Intelligence X100 Series brings exciting performance improvements critical for AI at the far edge to the data center

The Perfect Solution for Local AI - SiFive Blog

SiFive_intelligence-gen2_Blog_1000x500-v1.jpg

Developer enablement updates for RISC-V infrastructure: Red Hat RHEL on HiFive Premier P550, NVIDIA CUDA port, RVA23 ratification, Canonical Ubuntu support, and RISE Project advancements.

![Premier P550 Board](https://images.prismic.io/sifive/aJqr6aTt2nPbaMH9_SiFive_NVIDIA-CUDA_Blog_1000x500.jpg?auto=format,compress)
**By Ian Ferguson, V.P. of Business Development, SiFive** 

When I joined SiFive in early 2024, the initial focus (which has since broadened) was to explore how best to drive adoption of SiFive’s [RISC-V technology](https://www.sifive.com/about/risc-v-history) into system-on-chip components targeting [data center use cases](https://www.sifive.com/solutions/data-center). Efforts to introduce new technologies, and to displace long-term incumbents, are not initiatives that succeed in just a few quarters. These programs take years to execute. I speak from experience: in early 2008, a few colleagues and I, described internally as “rogues” (though we preferred “visionaries”), started the initiative to drive Arm into the server market.

Upon arriving at SiFive, it was clear that our CPU roadmap would, over time, catch up with the single-thread performance capabilities of products from incumbent suppliers. But three other areas also needed to be addressed to truly open this market to a broader set of customers, beyond just one or two early [innovators](https://medium.com/@samuelvandeth/crossing-the-chasm-162802d1cf27).

The first area I’ll explore in this blog post is enabling the software developer community. I’ll leave the other two as a mystery (for now) and return to them in future posts later this year.

**Three Numbers for You:**

**90**

**4**

**12,800**


What do these numbers mean? Today, projections show that NVIDIA “owns” 90% of GPU-based neural network training. They boast a developer base exceeding four million people. And, on average, 12,800 lines of code are added, modified, or deleted in the Linux kernel each day.

A few folks have posited that "hardware is cool again," but fundamentally, without strong software support, the effort for companies to adopt new hardware technologies is simply too great.

In May, [Red Hat announced](https://www.redhat.com/en/blog/red-hat-partners-with-sifive-for-risc-v-developer-preview-for-red-hat-enterprise-linux-10) the release of a developer edition of Red Hat Enterprise Linux (RHEL) for use on SiFive’s latest [RISC-V developer board, the HiFive Premier P550](https://www.sifive.com/boards/hifive-premier-p550). Alongside this, they also made RISC-V source code available for the [CentOS community](https://blog.centos.org/2025/05/initial-centos-support-for-risc-v/).

Then in July 2025, NVIDIA announced it is porting CUDA to RISC-V, using the HiFive Premier P550 as the starting point for this work. While no timeline was shared for when the code will be available, the announcement has already generated significant interest across the press, customer base, and competitor landscape.

At this point, I can’t expand beyond what’s already in the public domain. But there's an excellent analysis by **Joe Byrne** posted [here](https://xpu.pub/2025/07/23/cuda-risc-v/) that gives helpful context. As Joe writes:

“NVIDIA is making RISC-V a supported architecture, alongside Arm and x86—which means that, once the code is available, companies will be able to select a RISC-V CPU to be coupled alongside a NVIDIA GPGPU.”

RISC-V International also just released a [blog](https://riscv.org/blog/2025/08/nvidia-cuda-rva23/) based on a discussion with Frans Sijstermans, the NVIDIA executive who revealed the news at the [RISC-V Summit China](https://riscv-summit.com/en/).

**Common Themes from Red Hat and NVIDIA**

I see three common threads across Red Hat’s and NVIDIA’s announcements:

**Future-Readiness:** Both companies are preparing for a future where RISC-V server hardware is widely deployed. They want to be ready for that reality.

**Platform of Choice:** Both are basing their initial work on the [HiFive Premier P550 board](https://www.sifive.com/boards/hifive-premier-p550). I believe that’s due to its high performance relative to other RISC-V boards, its stability, and the excellent work our engineering team is doing to upstream open source code—plus the performance and expansion capabilities of the hardware. Having this powerful capability in silicon is enabling many developers to get “hands-on” with RISC-V in new ways.

**RVA23 Milestone:** The ratification of the [RVA23 profile](https://riscv.org/riscv-news/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/) has had a galvanizing effect. Large ecosystem players want to target platforms that are supported by multiple vendors with a consistent processor architecture. A common instruction set that software can count on is key to making that possible.

It would be remiss not to recognize the pioneering work Canonical has done in the RISC-V ecosystem—making Ubuntu a first-class citizen for RISC-V.

The combined investments of these industry heavyweights, along with support from many companies participating in the [RISE Project](https://riseproject.dev/), are bringing us closer to a reality where customers can choose among three processor architectures. Barriers for system builders, software developers, and component vendors are being removed—almost daily.

RISC-V is unique in its openness. Vendors can build chips for narrow, highly specialized vertical markets. NVIDIA clearly sees an opportunity here to extend CUDA into entirely new domains—something that would be much harder to do with other commercial ISAs designed to serve broad, generic markets.

The power of CUDA combined with the unlimited future of RISC-V is truly exciting.

SiFive recently celebrated our [**ten-year anniversary**](https://www.sifive.com/blog/sifive-celebrates-10-years-as-your-trusted-partner), and we continue to push the boundaries of what’s possible with RISC-V. As always, we want to hear from you—your ideas, your innovations, and your challenges.

We’ll all come together at the RISC-V Summit in Santa Clara this October, where I’m looking forward to some great presentations and discussions. Let’s use that as a platform to expand the conversation and accelerate momentum even further.

Ultimately, it’s now up to the RISC-V community to prove NVIDIA right.

Discover how SiFive is advancing RISC-V for Infrastructure, with Red Hat and NVIDIA enabling powerful software support, the HiFive Premier P550 platform, and a rapidly growing developer ecosystem.

RISC-V for Infrastructure: For Now, It’s All About the Developer

SiFive_NVIDIA-CUDA_Blog_1000x500.jpg

![ten year logo](https://images.prismic.io/sifive/aIKcBlGsbswqTO20_SiFive_10years_Blog_Social_1920x1920-v1.2.jpg?auto=format,compress)

SiFive was founded with a simple but ambitious goal: to help bring the potential of RISC-V to the world and support a more open, accessible future for custom silicon design. Ten years later, we’re honored to have played a role in the remarkable growth of the RISC-V ecosystem—an achievement made possible by the support, collaboration, and belief of a global community.

**From Lab to Leadership**

While we’re proud of milestones like over 400 design wins and more than 10 billion cores powered by SiFive technology in the market, we know these results are part of a much bigger story.

The progress of RISC-V has far exceeded early expectations. We’re grateful to have contributed to this journey, not only by advancing RISC-V technology, but also by contributing to and supporting the collaborative environment that makes open standards thrive. Our employees, past and present, have built a company with a culture of innovation, cooperation, and a relentless focus on solving customer challenges. 

**Responding to Rapid Change**

Over the past decade, the industry has seen rapid change—particularly with the rapid rise of AI and the transformation of the automotive landscape. We’ve worked closely with our partners and customers to adapt our IP offerings to meet new challenges: enabling and supporting AI acceleration, providing zonal architectures for automotive, and delivering energy-efficient, high-performance solutions tailored to emerging market needs.

From [data centers](https://www.sifive.com/solutions/data-center) to [edge computing](https://www.sifive.com/solutions/edge-computing), [aerospace](https://www.sifive.com/solutions/aerospace-defense) to [IoT](https://www.sifive.com/solutions/iot-embedded), we’re fortunate to be working closely with innovative companies across a wide range of industries. Eight of the world’s top ten semiconductor companies now use SiFive IP in their products, and we continue to learn from and grow with every customer we partner with. All of the Magnificent 7 have RISC-V projects underway and we are proud to be working with most of them. 

**Highlights from the Past 10 Years**

Our journey has been shaped by the dedication of our team and the close cooperation of the RISC-V community. Some milestones we’re proud of can be seen in the infographic below.

![10 Year Infographic](https://images.prismic.io/sifive/aIPgQ1GsbswqTRIP_SiFive-10Years-Infographic-Final.jpg?auto=format,compress)

Throughout this time, we’ve continued contributing to RISC-V International and open software stacks, from Android to IREE, WorldGuard and to the RISE Project, always with the belief that openness accelerates innovation.

**Looking Ahead: A Shared Vision for the Future**

As we enter our second decade, we’re excited for what’s next—not only for SiFive but for the entire RISC-V ecosystem. Opportunities in every application continue to expand, and we’re committed to supporting our partners every step of the way. Whatever the application, we aim to become a trusted partner and that goal affects every part of our business.

**Thank You**

This milestone is not ours alone. It is shared with the engineers, developers, researchers, customers, investors, and advocates who have shared our belief that a more open approach to computing is not only possible—but necessary. The early adopters who saw promise, and entrusted us to deliver, continue to show us the way forward as they are joined by the world’s largest semiconductor and hyperscale companies. 
To everyone who has supported SiFive over the past ten years: **THANK YOU!**
 
Your trust and collaboration continue to inspire us every day.

Here’s to the next decade of innovation, together.



Screenshot 2025-07-22 at 9.16.03 PM.png

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Building the Future of AI on Intelligent Accelerators

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The Perfect Solution for Local AI