Resources & Support

SiFive Press Room

November 01, 2023

MEDIA ALERT: SiFive to Participate in Numerous Speaking Sessions and Sponsor Developer Zone at RISC-V Summit North America 2023

WHAT: SiFive will be onsite at the annual RISC-V Summit, scheduled for Nov. 6 – 8, 2023 in Santa Clara, CA. The Summit brings together the fast-growing RISC-V ecosystem for several days of discussion. SiFive’s Krste Asanović will deliver the RISC-V ISA: State of the Union in his keynote and will address recent developments in RISC-V standards and the roadmap for future advancements.

SiFive will also host a series of technical sessions on RISC-V cryptography extensions, RVV C intrinsic API v. 1.0, RISC-V N-Trace specifications, LLVM RISC-V compilers, and more. At the event, SiFive experts can speak to the company’s broad Core IP portfolio, including the company’s most recent products, the SiFive Performance P870 and SiFive Intelligence X390, which were designed to address new requirements for high-performance compute. SiFive is a sponsor of the Developer Zone where attendees can meet with SiFive technical experts and see the latest development boards.

Also make sure to check out SiFive’s speaking sessions at the show: • Monday, Nov. 6 (Member Day): • 1 p.m. PST: Member Day Session: Future Direction of RISC-V Cryptography Extensions – Richard Newell, Microchip Technology Inc & Nicholas Bruine, SiFive • 1:30 p.m. PST: Member Day Session: Unprivileged Specification ISA Committee – Krste Asanović, SiFive & Earl Killian, Aril Inc. • 2 p.m. PST: Member Day Session: Discovering the RVV C Intrinsic API v. 1.0 – Eop Chen, SiFive • 3 p.m. PST: Member Day Session: RISC-V N-Trace Specification – An Overview • Tuesday, Nov. 7: • 11:50 a.m. PST: Making LLVM RISC-V Compiler More Performant for Everyone SiFive • 2:35 p.m. PST: Challenges in Porting Android to RISC-V – Samuel Holland, SiFive • Wednesday, Nov. 8: • 9 a.m. PST: Keynote: RISC-V ISA: State of the Union – Krste Asanović, RISC-V founder, SiFIve Chief Architect & RISC-V International BOD

WHO: SiFive WHEN: Nov. 6-8, 2023

Schedule here.

WHERE: RISC-V Summit North America Santa Clara Convention Center 5001 Great America Parkway Santa Clara, California, 95054

Registration for the event is still open, register today.

To schedule a meeting with SiFive onsite at the RISC-V Summit, please email: sifive@racepointglobal.com.

See more information on SiFive’s market-leading RISC-V IP portfolio, please visit SiFive.com.

Read more SiFive news

Upbeat Technology and SiFive Introduce Next-Gen Ultra-Low Power RISC-V MCU with AI Acceleration 
Blog Post
Upbeat Technology and SiFive Introduce Next-Gen Ultra-Low Power RISC-V MCU with AI Acceleration 
Upbeat Technology, a pioneer in ultra-low power compute, voice, and edge AI sensing solutions, and SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announce the UP201/UP301 family MCU, a next-generation dual-core RISC-V microcontroller designed for ultra-low power efficiency.
SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center
Blog Post
SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center
Further expanding SiFive’s lead in RISC-V AI IP, the company today launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products designed to accelerate AI workloads across thousands of potential applications.
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
Blog Post
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
Developer preview of Red Hat Enterprise Linux 10 on SiFive HiFive Premier P550 platform provides developers with a platform to optimize a new class of enterprise and cloud computing applications Boston, Mass. – May 20, 2025 – SiFive, the gold standard for RISC-V, today announced a collaboration with...