P570 Gen 3: A System Perspective

In the world of semiconductor announcements, the focus is usually "up and to the right", meaning more single-threaded performance and expanded system capabilities. Our January 2026 announcement regarding NVIDIA NVLink Fusion integration was a response to that thirst for top-tier performance.

However, CPU requirements span a spectrum of performance, power, and price points. For some segments, there is a need to deliver improved performance inside a different set of power and cost constraints. Systems based on these CPUs need credible roadmaps to effectively deliver new system capabilities. While some suppliers have abandoned the "low end," SiFive remains committed to innovation across the entire performance curve. Today’s announcement of the P570 Gen 3 Performance IP is focused on providing a significant performance-per-dollar and performance-per-joule boost for low-to-mid-range, Linux-capable systems.

While my colleague Ram Naik discusses the technical attributes of the core [link to blog], I want to look at this from an application perspective. I see two primary categories of use cases, which, in my simplistic view, look like:

1. Apps where our customer owns the software. To be more specific, the P570 IP is NOT exposed to the general developer. In this area, I am seeing interest in the P570 for use cases that include
   • SmartNICs: Offloading the main CPU in a system from handling networking tasks
   • Robotics Orchestration: With AI algorithms changing so rapidly, customers need a programmable engine to handle use cases that a customer’s NPU doesn’t recognize as well as to coordinate the ingestion of data into the NPU and transfer of modified data back into main memory. This transformation is analogous to the days when the PC industry drove technology. Inclusion of a PCI interface on chips increased the useful life of systems since new peripherals would appear first with PCI interface. Adding a programmable engine is, I feel, essential in providing that “get out of jail free” card for today’s (and tomorrow’s) AI platforms as the P570 provides the "future-proofing" that fixed-function hardware lacks.
2. Use of P570 as a general-purpose compute platform. In this case, the CPU is available to be programmed by developers. The P570 Gen 3 processor is compliant with the RVA23 profile which aligns with the software developments of leading independent software vendors like Canonical and Red Hat. Since those big companies are focused on high quality Linux for RVA23 based systems, there are also good versions of pure open-source Linux including CentOS and AlmaLinux. For this category of applications, we are seeing strong interest and commitments for use in designing:
   1. The primary processor in digital consumer applications: including set-top boxes and digital TVs. In addition to a high-quality Linux, I am delighted that we have a range of additional 3rd party partners working with us here. This includes:
      1. Imagination Technologies: A long-term partner that delivers proven GPUs and software stacks to drive screens.
      2. Debug: The compatibility of the debug interface on the P570 with that on the P450/P470 has enabled a simplified path for companies including Lauterbach to support the new core and provide an easy migration path for existing users of the P450/P470.
      3. OP-TEE: Security is top of mind for many companies. In fact, our job isn’t complete until it is top of mind for ALL companies! OP-TEE is a Trusted Execution Environment (TEE) designed as a companion to a non-secure Linux kernel. Historically created by Linaro for use by the Arm ecosystem, SiFive worked with RISE late last year to get this software ported over to RISC-V. OP-TEE implements a TEE Internal Core API which is the API exposed to Trusted Applications and a TEE Client API, which is the API describing how to communicate with a TEE. A massive shout out to RISCstar for their work to date on making this a reality.

      There are some additional 3rd parties that are optimizing their software for RISC-V Vectors (RVV) which I hope to be able to announce shortly. You can find out more about how 3rd parties are viewing the P570 announcement.

   2. EdgeAI platforms: This core is a good foundational block to create general purpose EdgeAI computers for IoT platforms, including industrial gateways, ATMs and digital signage.

After my three decades in this industry, involved in various parts of the semiconductor value chain, including intellectual property, chip development and systems, I am still constantly surprised by the ecosystem's creativity. Open standards like RISC-V simply make execution faster and better.

I cannot wait to see the innovative chips and systems the community builds with the P570 Gen 3!