Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications

Introduction

The heart of SiFive is RISC-V, the ISA invented by SiFive’s founders 5 years prior to starting the company! SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. In technology, evolution is not merely a timeline of random changes. It is a well-planned ladder of interdependent milestones. Each step creates a new set of environmental conditions that make the next, more complex, leap inevitable. Winning requires flexibility and innovation to adapt. Both are core values of SiFive and RISC-V.

Which brings me to the topic of the evolution of SiFive’s out-of-order cores and this moment in time that brings us to the exciting launch of third generation P550 and P570 performance core IP.

History of SiFive’s P500 series

The first generation P550 was SiFive’s first out-of-order core featuring a 13-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA; the baseline "general" 64-bit profile with bit-manipulation for performance improvements. This IP is the heart of the HiFive Premier P550 development board, and has been instrumental to furthering the developer momentum within the RISC‑V software ecosystem.

The rise of applications requiring mixed scalar and vector workloads led to the second generation of products: P450/P470. The second generation carried forward the same refined out-of-order architecture and enhanced it with a vector pipeline along with a more sophisticated load and store unit to balance the scalar and vector loads/stores.

The third generation introduces a 3-level memory hierarchy relative to the first and second generations. Besides the instruction and data caches, P550/P570 introduces an optional level 2 cache that is shared across up to 4 cores within a single cluster and a level 3 cache that is shared across up to 4 clusters. When compared to the second generation with a private level 2 cache per core, this hierarchy makes available the entire shared cache within a core complex to a single core if running a single thread, with other cores idle. This helps with single threaded performance which is important in low latency scenarios like opening applications, where quality of service is critical to the use case.

P550/P570 doubles the memory bandwidth. A wider bus allows for more data to be transferred per clock cycle. At the same time, customers can now configure level 2 and level 3 cache buffers to manage "in-flight" memory operations to cover latencies.

There were enhancements in other areas too, especially in power management and interrupt architecture. Stay tuned for a detailed technology explainer for a deeper dive in the third generation architecture.

The architecture also kept pace with the evolution of RISC-V ISA from RV64GBC to RVA22; ensuring portability for rich operating systems like Linux, defining a minimum mandatory set of ISA features for 64-bit application processors that included the ‘H’ (Hypervisor) extension for virtualization. With an eye on the next major ISA evolution- the RVA23 ISA profile, the second generation P470/P450 built in incremental extensions supporting vector and vector crypto compliant with RVV1.0, the first ratified specification for vector processing in the RISC-V. As a result, the ISA profile for the second generation SiFive Performance IP was more like RVA22++ (not an official RVA profile name). Extending far beyond the mandatory RVA22 profile and with many optional extra ISA extensions the Second Generation P470/P450 were very close to what became the full RVA23 profile, which was an important part of getting ready for the next progressive step in ISA evolution, the fully ratified RVA23 profile.

RVA23

Ratified in late 2024, RVA23 is a major release designed for high-performance computing, mobile, and workstation hardware. It is the foundation for the RISC-V Android ABI. It makes mandatory extensions for vector, security/hypervisor and cryptography, while adding optional extensions for security(examples: Landing pads and shadow stacks) and performance (half precision floating point). The table below shows the full extent of RVA23 ISA profile and SiFive product inclusion.

The shift to RVA23 allows software providers like Canonical (Ubuntu) and Red Hat to create standardized, optimized binaries that will run on any compliant RVA23 CPU, eliminating the need for custom compilations for every chip. RVA23 is a pivotal milestone in the continued and inevitable progression of the RISC-V ecosystem as it forms the basis of software portability across diverse RISC-V hardware implementations. Looking back a few years from now, I believe this is the critical piece that will be seen as galvanizing the adoption of RISC-V.

P570 Gen3- A notable milestone in the evolution of SiFive RISC-V out of order cores

The third generation P550/P570 inherits its architecture pedigree from the first generation IP, while building on top of the second generation P450/P470 improvements, with further enhancements in power, leakage and performance (see below charts). Most importantly, the third generation IP not only complies with the RVA23 profile but we actually extended beyond. In total, beyond the extensions required for compliance, the third generation P550/P570 includes as the baseline all the additional mandatory extensions. We have added support for additional product extensions for improved security, vector crypto, increased vector throughput, control transfer records, and support for more AI datatypes (like FP16/BF16).

The third generation P570 achieves 13% higher Specint_rate2017/GHz and greater than 2x Geekbench/GHz when compared to the first generation P550.

The third generation P570 achieves 13% dynamic power savings and greater than 50% savings in leakage compared to the first generation P550(Note: this is on TSMC12 node). SiFive has implemented this core on both TSMC3 and TSMC12- to serve as two bookends of cost and performance.

Compared to the second generation, the vector pipeline for the third generation is augmented with vector dot product extensions developed first by SiFive and now donated to RISC-V International for fast track ratification. As a result of these extensions, you see significant performance improvements on certain AI workloads, especially those using convolutional neural networks (CNNs) for image classification, object detection and image segmentation. This is evident when comparing certain Geekbench sub tests between second and third generation. As an example, on object detection we see a 21X improvement vs Gen1 P550 and 4.5x vs Gen2 P470.

Vector Crypto Performance

Vector crypto performance is critical for modern CPUs. It enables parallelization of high throughput encryption, decryption, and hashing tasks without overwhelming the core, making it a must have for blockchain, secure communication, and cloud storage.

The third generation P570 has implemented RISC-V ShangMi (SM) crypto extensions to accelerate Chinese national standard cryptographic algorithms (SM3, SM4) on RISC-V cores. They include ratified vectorized extensions (Zvksed, Zvksh) providing efficient, standardized acceleration for SM4 block ciphers and SM3 hash functions.

P570 also implements hardware extensions Zvkned and Zvknhb to speed up the vector crypto NIST suite for AES and SHA-256, SHA-512 algorithms respectively.

Conclusion

The third generation P550/P570 has meticulously evolved from its proven first generation lineage by carefully planning in three areas:

1. Enhancing the architecture to include a 128-bit vector pipeline for a balanced scalar and vector execution with the inclusion of vector dot product extensions
2. Upgrading to a modern ISA and RVA23 profile to propel the RISC-V ecosystem by enabling software developers to build for a wider installed base without worrying about compatibility
3. Providing generational improvements in power and performance

This provides a unique design point for out-of order cores that offers customers very competitive power and performance efficiency, while delivering AI natively.

As I said earlier, at SiFive product evolution is a well planned ladder of interdependent milestones. The third generation P550/P570 is a great case in point.

The flexibility of RISC-V ISA combined with the innovative approaches at SiFive allow us to evolve our products rapidly to meet environmental needs. The best is yet to come. Stay tuned.

• Download the P570 product brief

• Explore the capabilities and potential of the SiFive Performance P500 Series.

• You can learn more in our video featuring Krste Asanovic