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SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

The SiFive blog is your go-to-source for updates on all things RISC-V including processor IP, chip architecture, software and other innovations. Whether you’re producing the next great consumer device, optimizing a datacenter or building next-generation autos check back often to hear the latest from our experts.

Open Standards Work!

Dec 18, 2018
We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to S...
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Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Oct 30, 2018
Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architect...
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Last Week in RISC-V: October 19, 2018

Oct 19, 2018
It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Tes...
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Last Week in RISC-V: October 12, 2018

Oct 12, 2018
This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're loo...
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Last Week in RISC-V: Sept 28, 2018

Sep 28, 2018
I spent too much time writing my single entry this week so it's all I have. The issue itself is somewhat complex, so I thought it warranted a deep dive. Relaxing R_RISCV_PCREL_* in the Presence of Addends Jim recently found an issue with our ELF relocation scheme. While technically it's a somewhat...
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Last Week in RISC-V: Sept 21, 2018

Sep 21, 2018
Introduction to Linux Kernel Development For those of you interested in getting involved in the RISC-V Linux kernel porting effort, I wrote a short email that links to the various sources of information that might help people get started. Developer Room at FOSDEM I submitted a proposal for a RISC-V ...
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