SiFive System IP
IOMMU Gen 2

Full Spec Compliance: Built in strict accordance with the RISC-V IOMMU 1.0.1 architecture standard.

Distributed Microarchitecture: Centralized main IOMMU core coupled with up to 8 distributed I/O translation lookaside buffers (IOTLBs). splits address translation into multi tier infrastructure. Large translation look aside buffer can orchestrate parallel page table walkers (up to 32 instances) to navigate memory structures with minimal latency.

Advanced Virtualization: Supports single stage translation and nested translation for first and second stage.

Flexible Paging Schemes: Full hardware support for standard RISC-V Sv39, Sv48 and Sv57 paging rules.

Industry Standard Interfaces: Arm® AMBA® Distributed Translation Interface (DTI-ATSv2 and DTI-ATSv3) protocol support for PCIe ATS standard mechanisms.

Security Partitioning: Integrates up to 4 independent logical ways, with robust isolation across distinct software worlds.

Deep WorldGuard Solution Integration: Enforces system isolation and security between Host and Guests.

Quality of Service (QoS): Native Resource Capacity ID (RCID) propagation to enforce strict cache capacity and bandwidth allocation policies.

Integrated Diagnostics: Comprehensive Hardware Performance Monitor (HPM) utilizing independent 40-bit event counters per domain.

Comprehensive PCIe ATS and PRI Support: Provides strong protection from buggy or malicious device drivers and misbehaving IO devices and enables 32b legacy IO to access > 4GB address space.