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SiFive Accelerator Control Unit (ACU) Solutions

Offload host CPUs, optimize data movement, & future-proof custom AI engines with a programmable RISC-V based control layer

Intelligent Orchestration for Custom AI

In addition to providing Edge-to-Datacenter inference solutions, SiFive Intelligence IP is designed to serve as an ideal Accelerator Control Unit (ACU), combining programmable RISC-V scalar and vector processing and control capabilities with direct, high-speed, high-bandwidth connectivity for optimized data movement. This allows designers to focus on their custom accelerator's core data processing potentials.

An ACU reduces, and can eliminate or replace, the system level host processor’s low level orchestration burden and provides better support for evolving workloads, allowing designers to focus on their custom accelerator’s core data processing capabilities now and in the future.

The Evolution of Accelerator Control

Traditional custom accelerators rely on fixed state machines and shared system buses, leading to high host CPU overhead, memory bottlenecks, and rigid hardware limitations.

Traditional Approach has Challenges 

Legacy system architectures are designed around a host processor that manages a custom accelerator through a dedicated system bus, mapped control registers, state machine, and Direct Memory Access (DMA).

Challenges:

  • Fixed data manipulation and processing capabilities
  • Large data transfers over a shared bus
  • High latency for communication and data sharing
  • Complex and fixed control logic
  • Nonstandard to program and hard to update

Traditional Approach

Intelligent ACU Orchestration 

The SiFive Intelligence™ Accelerator Control Unit (ACU) solution shifts system management to a dedicated, programmable RISC-V front-end controller. By taking over task scheduling, resource allocation, command dispatch, and data formatting, the ACU enables your host processor to focus on primary application execution. Alternatively, the ACU can serve as the host processor itself, as the SiFive Intelligence Series ACU solution supports RTOS and Linux environments.

SiFive ACU Solution Benefits

SiFive Intelligence cores offer additional compute functionality with attached vector units and can offload or provide new functionality not planned when the custom accelerator was originally developed.

Key Advantages

  • Future-Proof Flexibility: Replace rigid state machines with a programmable RISC-V core. Deploy software and firmware patches to fix bugs or add functionality without costly hardware re-spins.
  • Complete Host Offloading: The ACU acts as an intelligent orchestration layer, allowing the custom accelerator engine's data throughput to operate independently of the main processor.
  • Fallback Vector Assist: SiFive Intelligence cores feature vector units to handle nonmatrix operations like activation functions, Softmax, or entirely new algorithms your custom accelerator wasn’t originally designed for.
  • Open Ecosystem: Built on full RISC-V ISA compatibility, the ACU allows you to leverage an industry-supported, open-standard software stack to dramatically reduce time to market.

SiFive Intelligent Accelerator Approach

SiFive Benefits for Custom Accelerator Design

Classic architectures throttle performance by forcing massive data transfers and control commands over a single shared bus. SiFive IP eliminates this bottleneck with three complementary, direct connections to the custom accelerator:

  • VCIX (High-Bandwidth Data Movement): Directly interfaces to the SiFive Intelligence core vector registers. It streams packed tensor and matrix datasets straight into the custom hardware accelerator at core clock frequency to keep heavy compute engines constantly fed.
  • SSCI (Low-Latency Control): Directly interfaces to the SiFive Intelligence scalar CPU execution pipeline. It keeps your engine responsive by dispatching custom scalar instructions and handling data-dependent decisions with single-cycle round trips.
  • CLP (Core Local Port): Bypasses the L2 memory to cache subsystem to provide the AI core with high-bandwidth, low-latency access to local or customer RAM.

Intelligent Orchestration for Custom Accelerators 

ACU Rule #1: Keep the accelerator fed

ACU Rule #2: Keep control responsive

When paired with SiFive Intelligence X100, X200, or X300 series cores, the SSCI, VCIX, and CLP interfaces transform the custom accelerator engine to an Intelligently Orchestrated Engine that decouples the custom accelerator's data throughput and execution from the main host processor.

How the Intelligence Series orchestration works:

  1. Move or stage the data to the Custom Accelerator Engine. The ACU can access system memory through its own memory path for bulk data movement. When data needs to pass through the ACU, its vector unit can stage or transfer it over VCIX. The ACU can also use CLP to reach local accelerator memory.
  2. Launch the operation. Once the required data is ready, the ACU scalar core sends an SSCI custom instruction to configure the accelerator and trigger the workload.
  3. Keep useful work moving. While the custom accelerator engine handles its primary operation, the ACU can perform additional vector work such as data formatting, activation functions, Softmax, or other algorithms not built into the custom engine, while also coordinating subsequent work.

SiFive Intelligent Orchestration

Size the Right ACU for Your Workload

Sizing the right SiFive Intelligence core for an Accelerator Control Unit (ACU) solution depends on balancing three primary factors:

  • Data Movement Bandwidth
  • Control Complexity
  • Auxiliary/Fallback Compute Needs

The vector length (VLEN) and datapath width (DLEN) of the selected core determine both the data movement bandwidth available over coprocessor interfaces and the onboard computational capability of the ACU.

  • X100 Series (Control-Heavy & Compact): Ideal for accelerators needing low-latency instruction dispatch over SSCI without wasting die area. Runs efficiently on Tightly Coupled Memory (TCM/SRAM) with an RTOS.
  • X200 & X300 Series (Data-Heavy & Fallback Compute): Ideal for continuous, high-bandwidth input streaming. Wider VCIX vector datapath (256-bit, 512-bit, or 1024-bit VLEN) for greater data transfer capacity. These cores feature a full MMU, RVA23.1 profile support for Linux environments, and robust vector units to handle demanding fallback workloads.

Ready to streamline your hardware integration, accelerate your design process and maximize system efficiency? Contact the SiFive sales team today to schedule an architecture review and explore how our Intelligence Series IP can accelerate your next datacenter, IoT, Automotive, Robotics or other Physical AI technology breakthrough.

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SiFive Intelligence Family

X100 Series
Intelligence
  • 32-bit or 64-bit CPU
  • 128-bit Vector Length
  • SSCI and VCIX
View X100 Series
X200 Series
Intelligence
  • 512-bit Vector Length
  • Single Vector ALU
  • SSCI and VCIX (1024-bit)
View X200 Series
X300 Series
Intelligence
  • 1024-bit Vector Length
  • Single/Dual Vector ALU
  • SSCI and VCIX (2048-bit)
View X300 Series

SiFive ACU Solutions: Learn More

SiFive Intelligence IP - Use Case: Accelerator Control Unit (ACU)
SiFive Intelligence IP - Use Case: Accelerator Control Unit (ACU)
SiFive 2nd Generation Intelligence Technology Explainer
SiFive 2nd Generation Intelligence Technology Explainer

Discover Customer Results

Case Study: Accelerator Control Unit Use Case

Tier 1 US Semiconductor Company Licensed SiFive X100 for Industrial Edge AI Applications.

View the Case Study

Case Study: Google Datacenter

SiFive Intelligence X280 Gen 1 as AI Compute Host

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Next Steps for Custom Accelerator Innovation

Optimizing custom accelerator control is essential for modern SoC success.

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