Beyond the CPU and GPU: SiFive in Datacenter Infrastructure

How embedded RISC-V processors in NICs, retimers, optics, switches, and security chips are overcoming modern scaling limits

Scaling AI clusters to 1.6T and beyond is making physical interconnects one of the datacenter's most pressing constraints. Architects must hold 800G optical modules to tight power budgets today (roughly 8–18W per module) while preparing for a 1.6T future where copper reach and signal integrity become limiting. While CPUs and GPUs execute the math, they rely entirely on embedded infrastructure to manage this underlying fabric. Hardware teams are already deploying SiFive RISC-V cores in commercial switches, transceivers, and SSDs, and SiFive IP has shipped in more than 10 billion cores with 500+ design wins across all markets.

Pick a single bit of data leaving a server or accelerator and follow it across the rack. It passes through a SmartNIC or DPU, gets cleaned up by a retimer, turns into light inside an optical module, crosses a switch or two, and arrives at another node—all while a management chip keeps watch over the whole platform.

Every one of those stops has its own dedicated processor.

The new physics of rack silicon

As AI racks scale, four drivers are forcing a redesign of infrastructure silicon:

• 800G today, 1.6T+ next: Optical interconnects are moving deeper into the AI rack rather than remaining confined to traditional scale-out fabrics. With the coming transition to 1.6T speeds, copper traces face severe reach and signal-integrity penalties, driving optics directly adjacent to switch silicon via linear pluggable optics (LPO) and co-packaged optics (CPO).
• Every watt counts: An 800G pluggable module draws roughly 13–18W with a DSP¹ and about 8–9W with linear drive.² Across tens of thousands of ports, every milliwatt matters, so embedded controllers must be small and efficient, with custom sensor and control loops built into the core.
• Switches are taking on compute: The Ultra Accelerator Link (UALink) 2.0 specification adds in-network compute for collective operations (such as reductions across accelerators) and a manageability model built on gNMI, YANG, SAI, and Redfish.³ The switch die now needs real-time telemetry cores, a Linux-capable management host, and dedicated control logic to orchestrate the compute engines.
• Security moves onto standard modules: The OCP Data Center Secure Control Module (DC-SCM) specification moves management and security onto a standard module,⁴ and the leading open roots of trust are built on RISC-V: Caliptra embeds an open-source RISC-V core,⁵ and OpenTitan is now shipping in production.⁶

Why customization wins

Closed instruction set architectures were built for generic processing. A configurable, open ISA addresses their trade-offs in rack silicon and gives hyperscalers and other system developers the vendor-neutral foundation they increasingly want.

• Custom instructions where they matter: Closed ISAs generally limit custom extensions to a small number of cores. RISC-V is designed to be extended, so designers can add instructions for photonics, SerDes adaptation, telemetry, or crypto primitives and expose them to firmware through the standard RISC-V toolchain flow.
• Right-sized silicon: General-purpose cores often include fixed features that infrastructure workloads don't need, adding area and power. With configurable cores, designers can size caches, vector lengths, and core counts to the job.
• One ISA family across the die: Standardizing on RISC-V replaces fragmented proprietary cores with a single architecture spanning sub-milliwatt controllers to multi-core Linux clusters that unify toolchains, debug flows, and security frameworks like SiFive WorldGuard™.

The SiFive compute portfolio

SiFive offers three IP families, with a complete core complex (core, uncore, and connectivity) configurable to the exact workload profile.

• Real-time control cores (Essential Family): Low-latency, deterministic microcontrollers for closed-loop thermal tuning, optical laser bias loops, retimer firmware, and hardware roots of trust.
• Vector and accelerator control cores (Intelligence Family): Vector-capable Accelerator Control Units (ACUs) that attach to a custom accelerator through SiFive's SSCI and VCIX coprocessor interfaces (direct, low-latency core-to-accelerator links) to sequence in-network compute and telemetry offloads.
• Application and management cores (Performance Family): Scalable, Linux-capable out-of-order processors for network OS agents, switch management hosts, and DPU control planes.

Mapping the rack

• NICs, SuperNICs and DPUs: Performance cores provide the Linux control plane, while Intelligence cores act as data-path event processors for transport and congestion control.
• Retimers: Essential cores run link-training and monitoring firmware, with a Performance core for management.
• Optics and CPO: Essential cores run module controllers and ring-tuning loops at milliwatt-class power. Intelligence cores can supervise the DSPs and apply custom photonic instructions.
• Scale-up and scale-out switches: Performance cores handle the management plane and on-die hosts, while Intelligence cores sequence in-network compute and telemetry offloads.
• BMC and root of trust: Essential cores with WorldGuard isolation sit alongside RISC-V roots of trust, bringing the same ISA to the whole security chip.

Core selection by application

Start with the sockets, not the chip

The next wave of cloud and AI infrastructure innovation is happening in the silicon around the compute node. Each NIC, retimer, optical module, switch, and security module is a different processor opportunity, with its own requirements for real-time control, management, and accelerator control. Start with the function each infrastructure block needs, rather than choosing a generic chip and working backward.

SiFive provides a complete portfolio of configurable RISC-V core complexes for those design points: the Essential family for deterministic control, the Intelligence family for accelerator control and in-network compute, and the Performance family for Linux-capable management. Designers can add workload-specific instructions, right-size caches and vector resources, and use one ISA, toolchain, and security model across the die. The result is silicon tuned to the workload, power, and latency requirements.

Contact SiFive to evaluate IP configurations for your NIC, retimer, optical module, switch, or security designs.

References

1. FS Community, "Advancing Optical Transceiver Technology: From 400G to 800G to 1.6T." https://community.fs.com/article/advancing-optical-transceiver-technology-from-400g-to-800g-to-16t.html
2. FS, 800G LPO module press release, Business Wire, Aug. 2025. https://www.businesswire.com/news/home/20250823684674/en
3. UALink Consortium, "Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G Performance," Apr. 2026.
4. https://www.businesswire.com/news/home/20260407620696/en/ Open Compute Project, Data Center Secure Control Module (DC-SCM) 2.0 specification. https://146a55aca6f00848c565-a7635525d40ac1c70300198708936b4e.ssl.cf1.rackcdn.com/images/437b280a3847b001b1609bd429908bf162a2b6df.pdf
5. CHIPS Alliance, "CHIPS Alliance Welcomes the Caliptra Open Source Root of Trust Project," Dec. 2022. https://chipsalliance.org/news/chips-alliance-welcomes-the-caliptra-open-source-root-of-trust-project/
6. lowRISC, "OpenTitan Root of Trust." https://lowrisc.org/opentitan/