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SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

The SiFive blog is your go-to-source for updates on all things RISC-V including processor IP, chip architecture, software and other innovations. Whether you’re producing the next great consumer device, optimizing a datacenter or building next-generation autos check back often to hear the latest from our experts.

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia

Our SiFive Tech Symposiums in Costa Rica and Mexico Underscore the Global Adoption of the RISC-V ISA in Industry and Academia

Feb 29, 2020
Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the co...
Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V

Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V

Feb 24, 2020
This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memor...
Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Jan 30, 2020
This is the third in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in system-on-chip (SoC) designs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportuni...
Part 1: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Part 1: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V

Jan 30, 2020
Domain-specific accelerators (DSAs) are becoming increasingly common in system-on-chip (SoC) designs. A DSA provides higher performance per watt by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packe...

With SiFive, We Can Change the World

Jan 27, 2020
A Note from Chris Lattner, New SVP of Platform Engineering My quest is to build beautiful things that help change the world, and I’ve been fortunate to spend the last 15 years in Silicon Valley, working with some of the major players shaping all sorts of technology. Today, I’m super excited to join ...
Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V

Part 2: High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V

Jan 21, 2020
This is the second in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in SoCs. Part #1 addressed the challenges associated with data transfers between DSAs and the core complex, and showed how RISC-V offers a unique opportunity to optimize fine-gra...