MEDIA ALERT: SiFive to Exhibit at the TSMC 2017 Open Innovation Platform Ecosystem Forum Pavilion Sept. 13

SANTA CLARA, Calif. – 9/12/2017

WHO: SiFive, the first fabless provider of customized, open-source-enabled semiconductors founded by the inventors of the RISC-V instruction set architecture.

WHEN: Wednesday, Sept. 13, 2017, during the TSMC 2017 Open Innovation Platform® (OIP) Ecosystem Forum. The Ecosystem Forum Pavilion will be open from 8 a.m. until 6 p.m.

WHERE:
Booth No. 215
Santa Clara Convention Center
5001 Great America Parkway
Halls C and D
Santa Clara, Calif. 95054

WHAT: SiFive will showcase its RISC-V based Coreplex IP, the most widely deployed RISC-V cores in the world and the lowest risk, easiest path to RISC-V. SiFive Coreplex IP are fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for next-generation SoC designs.

About SiFive

SiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit www.sifive.com.

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